creepsheep Posted February 24, 2012 Report Share Posted February 24, 2012 Hi, how to import vera file to uvm project? Quote Link to comment Share on other sites More sharing options...
Roman Posted February 24, 2012 Report Share Posted February 24, 2012 (edited) Hi, how to import vera file to uvm project?You may need to convert vera to SV first. see this http://www.uvmworld.org/forums/showthread.php?85-Converting-from-RVM-to-UVM Or study this webinar "Archived webinar - Migrating from VMM to the UVM" Attendees will learn about the migration planning requirements by walking through case studies of VMM and OVM migrations as well as Vera RVM to OVM/UVM. http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=474 Edited February 24, 2012 by Roman Quote Link to comment Share on other sites More sharing options...
janick Posted February 27, 2012 Report Share Posted February 27, 2012 If you are using VCS, you can load your OpenVera code along side your SystemVerilog code and it will be implicitly converted to SV and appear in the "openvera" package. It won't be using UVM though. It will be using VMM however so you can integrate it using the VMM/UVM interoperability package that ships with VCS. Quote Link to comment Share on other sites More sharing options...
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