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how to import vera file to uvm project?

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Hi, how to import vera file to uvm project?

You may need to convert vera to SV first.

see this


Or study this webinar "Archived webinar - Migrating from VMM to the UVM"

Attendees will learn about the migration planning requirements by walking through case studies of VMM and OVM migrations as well as Vera RVM to OVM/UVM.


Edited by Roman
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If you are using VCS, you can load your OpenVera code along side your SystemVerilog code and it will be implicitly converted to SV and appear in the "openvera" package. It won't be using UVM though. It will be using VMM however so you can integrate it using the VMM/UVM interoperability package that ships with VCS.

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