Delay in bitvector Output assignment

[Kishore17]

Hello All,

I am a beginner in SystemC, and I really need your help in solving a timing issue.

Please find my code attached :

datagen::datagen(sc_module_name nm)
    :sc_module(nm)
{
    cout<<"Constructor- datagen: "<< name() << endl;
    SC_THREAD(testgen);
    
}
void datagen::testgen(void)
{        
    busin_o="11111111";
    cout<< "-------------------------------------"<< endl;
    cout << "In dataGen::testgen: @"
         << sc_time_stamp()
         << " Busin in datagen: "<< busin_o       
         <<endl;      
        
    wait(1,SC_NS);
    cout<< sc_delta_count() << endl;    
    busin_o="00111111";
    cout<< "-------------------------------------"<< endl;
    cout << "In dataGen::testgen: @"
         << sc_time_stamp()
         << " Busin in datagen: "<< busin_o       
         <<endl;  
    
    wait(1,SC_NS);    
    busin_o="10000111";
    cout<< "-------------------------------------"<< endl;
    cout << "In dataGen::testgen: @"
         << sc_time_stamp()
         << " Busin in datagen: "<< busin_o       
         <<endl;  
    wait(1,SC_NS);
    busin_o="11111110";
    cout<< "-------------------------------------"<< endl;
    cout << "In dataGen::testgen: @"
         << sc_time_stamp()
         << " Busin in datagen: "<< busin_o       
         <<endl;
    cout<<"Intended end of simulation"<< endl;
    sc_stop();    
}

 

/* inputs2*/

inputs::inputs(sc_module_name inst)
    : sc_module(inst)
{    
    cout<<"Constructor- inputs: "<< name() <<endl;
    SC_METHOD(mydesign);
    sensitive << busin;
}
void inputs::mydesign()
{
    
    cout<< "-------------------------------------"<< endl;
    cout<<"Mydesign Activated @ "<<sc_time_stamp() <<endl;
    cout<< "-------------------------------------"<< endl;
    cout << "In Inputs::mydesign: @"
         << sc_time_stamp()
         << " Busin in Inputs: "<< busin       
         <<endl;  
    pout-> write(busin.read());
    cout << "In Inputs::mydesign: @"
         << sc_time_stamp()
         << " pout in Inputs: "<< pout
         <<endl;    
}

I have 2 issues

The first one is that mydesign block is being called twice @ 0 NS . (Can be seen in the screenshot)

The second is that the assignment of busin_o in the datagen file is happening with a delay of 1ns, whereas in inputs2.cpp, it is happening correctly. But again, the assignment of busin to pout is not happening at the same time as it happens after 1 ns. I am really confused as to why the behavior is like this. Any help is appreciated. I have a feeling that there is a small timing error somewhere, but I am not able to fix it. Please help me. All the codes are attached for further reference.

 

 

 

top2.h top2.cpp main2.cpp inputs2.h inputs2.cpp datagen2.h datagen2.cpp

[David Black]

By default all processes are called once at time zero.

Outputs on sc_signal are updated after the end of the delta cycle, which consumes no simulated time, but causes your method to be scheduled to run at the same time.

What appear to be blocking assignments to the programmer's eyes are in fact non-blocking assignments that schedule updates to happen at the end of the current delta cycle.

Assuming your bus_o is an sc_in<int>, which is a specialized sc_port< sc_signal_inout_if<int> >, then

bus_o = VALUE;

turns out to be equivalent to

bus_o->write(VALUE);

You need to learn how a co-operative multitasking event driven simulator works, and then you will fully understand.

[Kishore17]

Hello Mr. Black,

Thank you for the quick reply. I didn't quite understand what you exactly mean, but, I will try finding some material where i can learn how a co-operative multitasking event driven simulator works. But, did you mean to suggest that I use

bus_o->write(VALUE);

instead of

bus_o = VALUE;

I tried this, and I still get the same issue.

The question that still haunts me is , why does busin in my datagen file updates after 1ns? I can already see the value in inputs.cpp at 0 NS.

(Note : Inputs.cpp file receives busin value from datagen)

If you mean to say that the behavior is correct and I don't have to modify anything in my code, then it's all good.

Here, I am attaching datagen.h

SC_MODULE(datagen)
{
	public:	
	sc_out<sc_bv<8>> busin_o;	
	SC_CTOR(datagen);
	
	/*private:*/
	
	void testgen(void);
	void asTakt(void);
};

and inputs2.h

SC_MODULE(inputs)
{
	public:

	sc_in<sc_bv<8>> busin;
	sc_out<sc_bv<8>> pout;
	sc_out<sc_bv<8>> out;
	SC_CTOR(inputs);
	
	private:
	/* method*/
	void mydesign(void);
};

Please find the updated datagen.cpp, below

void datagen::testgen(void)
{		
	busin_o->write("11111111");
	cout<< "-------------------------------------"<< endl;
	cout << "In dataGen::testgen: @"
	     << sc_time_stamp()
	     << " Busin in datagen: "<< busin_o       
	     <<endl;  	
		
	wait(1,SC_NS);
	cout<< sc_delta_count() << endl;	
	busin_o->write("00111111");
	cout<< "-------------------------------------"<< endl;
	cout << "In dataGen::testgen: @"
	     << sc_time_stamp()
	     << " Busin in datagen: "<< busin_o       
	     <<endl;  
	
	wait(1,SC_NS);	
	busin_o->write("10000111");
	cout<< "-------------------------------------"<< endl;
	cout << "In dataGen::testgen: @"
	     << sc_time_stamp()
	     << " Busin in datagen: "<< busin_o       
	     <<endl;  
	wait(1,SC_NS);
	busin_o->write("11111110");
	cout<< "-------------------------------------"<< endl;
	cout << "In dataGen::testgen: @"
	     << sc_time_stamp()
	     << " Busin in datagen: "<< busin_o       
	     <<endl; 
	cout<<"Intended end of simulation"<< endl;
	sc_stop();	
}

And the inputs.cpp file still remains the same

inputs::inputs(sc_module_name inst)
	: sc_module(inst)
{	
	cout<<"Constructor- inputs: "<< name() <<endl;
	SC_METHOD(mydesign);
	sensitive << busin;
}
void inputs::mydesign()
{
	
	cout<< "-------------------------------------"<< endl;
	cout<<"Mydesign Activated @ "<<sc_time_stamp() <<endl;
	cout<< "-------------------------------------"<< endl;
	cout << "In Inputs::mydesign: @"
	     << sc_time_stamp()
	     << " Busin in Inputs: "<< busin       
	     <<endl;  
	pout-> write(busin.read());
	cout << "In Inputs::mydesign: @"
	     << sc_time_stamp()
	     << " pout in Inputs: "<< pout
	     <<endl;	
}

Please let me know if you find a problem with the code. Thanks a ton.

[David Black]

The behavior of SystemC matches what I expect, but is not what you are wanting to do.

My suggestion of how to write the output holds; however, that will not fix the error. My suggestion does make it likely that you might wonder what the write() method does and not fall prey to the assumption that assignment is simply assignment.

If you want to move the process to the end of the current delta-cycle, you can insert:

wait(SC_ZERO_TIME);

just prior to where you display the value after writing it.

If you want to avoid two calls to the SC_METHOD process, add:

dont_initialize();

after the SC_METHOD declaration. Do not apply this into the SC_THREAD though or that piece of code will never run.

Suggestion: Get a book on SystemC such as SystemC: From the Ground Up (I might be biased 😉) and read its description of the simulator.