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system bus interface


Khushi

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Hi Kushi,

A system bus interface must be connected to a mirrored system bus interface. Sometimes, system interfaces are used to connect clock and reset signals or side-band signals. An EDA tool behaves the same for system interfaces as for master/slave interfaces. It maps component ports onto logical ports, wires the logical port bits, and infers from that which ports from which component instances need to be wired in a generated netlist. There is no addressing associated with system interfaces.

Personally, I do no use system interfaces. In my opinion, the better approach is to map clock and reset in master and slave interfaces. This allows the use of abstractors to bridge between RTL and TLM descriptions. Clock and reset are needed at the RTL side but they are abstracted at the TLM side. This is not possible with system interfaces.

In general, to enable IP re-use, i.e. in IP-XACT terms to enable IP-XACT component reuse, an IP-XACT component shall not have bus interfaces specifically tailored to way the IP-XACT component is integrated in its context. I think this is a good way of thinking while creating IP-XACT components.

Best regards,
Erwin

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Thanks Erwin for the nice explanation.

I have an additional question here.  As you mentioned system interfaces are used to connect clock, reset and sidebands signals. How the system interfaces are helpful to connect these ? Are they provide some extra capabilities which is not there if we use normal(master/slave) interface connections or adhoc connections.

How the system group name in busdefs for the system bus interfaces are used in net-listing.

Thanks

Khushi 

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Hi Kushi,

The additional system interfaces allow you to make (clock, reset, sideband) connections in addition to the master/slave connections. So you can separately handle your clock/reset/sideband connectivity.

The system group names are not relevant for netlisting. They provide additional checking capabilities in IP-XACT.

Best regards,
Erwin

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