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Hi i'm new to the UVM worls.

I made a simple SystemVerilog program and a simple SystemVerilog env that extends the uvm_env (see them below):

Now, I want to compile it all in ncsim (version 11), so i did:

ncverilog -access +rwc -uvm -uvmhome /tools/uvm-1.1/uvm_lib/uvm_sv/ top.v top_program.sv

I get an error (it looks like the extends uvm_env is not allowed - as if the uvm packeage was not compiled???)

Compiling UVM package (uvm_pkg.sv) using uvmhome location /tools/uvm-1.1/uvm_lib/uvm_sv/

file: ../rtl/top.v

module worklib.top:v

errors: 0, warnings: 0

file: ../sv/top_program.sv

interface worklib.pp_seq_ifc:sv

errors: 0, warnings: 0

module worklib.pp_seq_bind0:sv

errors: 0, warnings: 0

class top_env extends uvm_env;

|

ncvlog: *E,SVNOTY (top_env.sv,4|28): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.

Any ideas what do i need to do?

here's the program and env:

//------ program -------

`include "top_if.sv"

program top_program;

`include "top_files.sv"

initial

begin

top_multi_env top_multi_env;

top_multi_env= new;

top_multi_env.start();

end

endprogram

//----- env ------

class top_env extends uvm_env;

string my_name;

function new(string name = "" );

my_name = name;

endfunction: new

....

endclass // top_env

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