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  1. Hi i'm new to the UVM worls. I made a simple SystemVerilog program and a simple SystemVerilog env that extends the uvm_env (see them below): Now, I want to compile it all in ncsim (version 11), so i did: ncverilog -access +rwc -uvm -uvmhome /tools/uvm-1.1/uvm_lib/uvm_sv/ top.v top_program.sv I get an error (it looks like the extends uvm_env is not allowed - as if the uvm packeage was not compiled???) Compiling UVM package (uvm_pkg.sv) using uvmhome location /tools/uvm-1.1/uvm_lib/uvm_sv/ file: ../rtl/top.v module worklib.top:v errors: 0, warnings:
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