UVM RAL implementation methodology for large designs

[rgarciaf071]

Hello,

I was wondering if are there any resources (papers, blogs, posts, best practices) about methodologies to implement UVM RAL for "large" designs (>100K registers and 50K rams)? I tried to do some research online but most of the results never cover "large" designs.

I have experience using RAL and doing some customisation to make it work in a particular environment (callbacks, maps, defining specialised registers, sequences) but most of them were "little" (1K regs and 100 rams)

I'm interested on any information about aspects such as:

• Reg model re-usability and portability at sub-system and system level environments
• Performance: How heavy is the register model, since having this much registers may have a huge performance penalty over simulations
• Dynamic reconfiguration (I know in 1.2 once your model is locked not much can be done)
• RAM modelling in RAL (since it the uvm_mem is different from uvm_reg)
• Register Model Partitioning at block level
• Register Model limitations on real projects usage
• Implementation of different sized registers and non uniform mapping
• General RAL limitations

Any material or hints on these topics is really appreciated
Apologies for the broad question

Thanks
-R

[rgarciaf071]

Since it seems this is not a interesting topic just in case someone is looking for information I came across these papers

http://www.verilab.com/files/litterick_register_final.pdf basically claims that factory registration of registers should be avoided to get better performance results

 Common issues and pitfalls