Element "arrays/array" of class configurable array in component IPXACT

[Bhargav]

HI,

What is the purpose of the element, ARRAYS present in component IPXACT definition.

In the above image, the port has name: defining physical port name, direction: wire direction, vectors: msb and lsb of the port.

What I don't understand is the purpose of arrays here. What it implies? Is it kind of multi dimensional port definition. If so, don't we already have indices, index defining them?

Thanks in advance,

Bhargav K

 

 

[kock]

Hi Bhargav,

The purpose of arrays is to describe arrays of ports. For instance, in SystemC you can write sc_out< sc_lv<32> > my_port[10]. Your IP-XACT fragment would  translate to SystemC as sc_in< sc_lv< 33 > > TAR_PRI_RD[6].

Best regards,
Erwin

[Bhargav]

Hi Erwin,

Thanks for that.

So basically, in RTL, it is indicating, some port  like: "input TAR_PRI_RD [32:0][5:0]"

I want to implement a multidimensional ports, or I have an array of array of ports in my verilog files, how do the get reflected in my IPXACT?

  Is the below one proper if I want to implement input [32:0][3:0][7:0][4:0] port in my RTL

  <ipxact:port>
            <ipxact:name>port</ipxact:name>
            <ipxact:wire>
                         <ipxact:direction>in</ipxact:direction>
                        <ipxact:vectors>
                              <ipxact:vector>
                                      <ipxact:left>32</ipxact:left>
                                     <ipxact:right>0</ipxact:right>
                             </ipxact:vector>
                       </ipxact:vectors>
            </ipxact:wire>
            <ipxact:arrays>
                          <ipxact:array>
                                 <ipxact:left>3</ipxact:left>
                                <ipxact:right>0</ipxact:right>
                         </ipxact:array>

                          <ipxact:array>
                                 <ipxact:left>7</ipxact:left>
                                <ipxact:right>0</ipxact:right>
                         </ipxact:array>

                         <ipxact:array>
                                 <ipxact:left>4</ipxact:left>
                                <ipxact:right>0</ipxact:right>
                         </ipxact:array>
            </ipxact:arrays>
    </ipxact:port>

 

Thanks in advance,

Bhargav

[kock]

Hi Bhargav,

Your IP-XACT fragment translates to input [32:0] port [3:0][7:0][4:0] in SystemVerilog. So the part in ipxact:vector is packed (left of the port name) and the part in ipxact:array is unpacked (right of the port name). If you want to represent input [32:0][3:0][7:0][4:0] port then all dimensions must go into ipxact:vectors and each dimension is a separate ipxact:vector.

Best regards,
Erwin