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Package for parametric design


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Hi,

I need to design & verify parametric design, such that my design & verif env will be instantiated twice, each time with different parameters.

I usually work with packages for my design, so all of parameters, structs etc are defined there.

My questions:

Is there a  way to write such package so same package will hold same parameter  with two different values? (different value for each instance)

Is there a robust way in uvm to verify such design?

Thanks!

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  • 4 years later...

I recently joined a similar team, and unfortunately the solution has been to put all the rtl localparam constants into their own file (not in a package), and include that everywhere it's needed (directly inside of verif classes, modules, etc). Those constants are dependent upon parameters, which means that every module and uvm component will have parameter proliferation. Also, because you can't have parameterized packages, the module port list use Verilog '95 style instead of ANSI 2001.

Would be nice if this feature request had some more activity, but I don't see much traction.
https://accellera.mantishub.io/view.php?id=4720

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There's a constant/localparam generated for every port's MSB and LSB, and many of them are dependent upon the module's parameters. This prevents using them in a 2001-style port list. IFF they didn't have that dependency, yes you simply wrap them in a package and import them prior to the port list.

The '95 style's lack of size or direction in the port list allows for `including the module's constants file prior to the input/output/inout list (which is sized) but after the parameter & port lists. 

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