clock generation in system c

[veeresh k]

Hi,

I have came across this counter example from other website.

Can u please tell me ,where have we intitialised the main clock.

I know the default time period is 1ps,but i am not getting the start of the clock is from which point.

I am not knowing the reason for its generation in waveform viewer.

Thank you.  

Below is the code:

#include "systemc.h"
#include "design.cpp"

int sc_main (int argc, char* argv[]) {
  sc_signal<bool>   clock;
  sc_signal<bool>   reset;
  sc_signal<bool>   enable;
  sc_signal<sc_uint<4> > counter_out;
  int i = 0;
  // Connect the DUT
  first_counter counter("COUNTER");
  counter.clock(clock);
  counter.reset(reset);
  counter.enable(enable);
  counter.counter_out(counter_out);

  sc_start(1, SC_NS);

  // Open VCD file
  sc_trace_file *wf = sc_create_vcd_trace_file("counter");
  // Dump the desired signals
  sc_trace(wf, clock, "clock");
  sc_trace(wf, reset, "reset");
  sc_trace(wf, enable, "enable");
  sc_trace(wf, counter_out, "count");

  // Initialize all variables
  reset = 0;       // initial value of reset
  enable = 0;      // initial value of enable
  for (i=0;i<5;i++) {
    clock = 0; 
    sc_start(1, SC_NS);
    clock = 1; 
    sc_start(1, SC_NS);
  }
  reset = 1;    // Assert the reset
  cout << "@" << sc_time_stamp() <<" Asserting reset\n" << endl;
  for (i=0;i<10;i++) {
    clock = 0; 
    sc_start(1, SC_NS);
    clock = 1; 
    sc_start(1, SC_NS);
  }
  reset = 0;    // De-assert the reset
  cout << "@" << sc_time_stamp() <<" De-Asserting reset\n" << endl;
  for (i=0;i<5;i++) {
    clock = 0; 
    sc_start(1, SC_NS);
    clock = 1; 
    sc_start(1, SC_NS);
  }
  cout << "@" << sc_time_stamp() <<" Asserting Enable\n" << endl;
  enable = 1;  // Assert enable
  for (i=0;i<20;i++) {
    clock = 0; 
    sc_start(1, SC_NS);
    clock = 1; 
    sc_start(1, SC_NS);
  }
  cout << "@" << sc_time_stamp() <<" De-Asserting Enable\n" << endl;
  enable = 0; // De-assert enable

  cout << "@" << sc_time_stamp() <<" Terminating simulation\n" << endl;
  sc_close_vcd_trace_file(wf);
  return 0;// Terminate simulation

}
 

 

[AmeyaVS]

Hello @veeresh k,

This example does not have a dedicated clock generator.

// These statements are what driving the clock signal to with High time of 1 ns and low time of 1 ns.
for (i=0;i<10;i++) {
  clock = 0; 
  sc_start(1, SC_NS);// Run simulation for 1 ns.
  clock = 1; 
  sc_start(1, SC_NS);// Run simulation for 1 ns.
}

What message you receive from the SystemC kernel refers to the timescale of 1 ps e.g.:

Info: (I702) default timescale unit used for tracing: 1 ps

You can get the SystemC API documentation for the sc_clock from here:

SystemC sc_clock api reference.

If you need a sample you can find a use-case reference here(though a little bit-dated):

https://github.com/AmeyaVS/SystemC_ramblings/blob/ff1a111063842bfcd6f5de6bb3db74917dc6331c/src/03_fir/firsytemmain.cpp#L26

Hope it helps.

Regards,

Ameya Vikram Singh

[veeresh k]

Hey ameya,

Thanx for the reply. ?

I have gone through documentation,but am not getting it completely.

By seeing the suggested api documentation from u,i am assuming that we will have a time period of 1ps along with 0.5 dutycycle by default and we are changing a bit of start value of clock by using sc_start(1,SC_NS) .We just got to declare it and mention it in trace file n we will get the waveform,ryt?

As u can see in below waveform,i know the reason for reset and enable changes,but the clock waveform reason i dint get.

N how can i change the clock waveform.Is it done by this sc_clock testclk("testclk",2,SC_NS,0.5,1,SC_NS).

Note:-In test clock i am just randomly taking the no.

 

.

 

[Eyck]

The clock cycle is determined by the wait(1, SC_NS) statements withing the for loop. This defines the duration of the high and low phase of the clock you are seeing. The timesacel message comes from the VCD trace file (more specifically its writer) saying that the recording resolution will be teh default of 1ps which might be too small for some cases. You may ignore this message or explicitly set the VCD timescale.

What Ameya is refering to is to replace the explicit clock generation with the SystemCs own sc_clock. This would alleviate you from describing the clock changes explicitly.

Actually in my opinion this is a really bad example for several reasons:

• it bloats the sc_main function with testbench coder
• it mixes periodic signal change generation (the for loops) with functional code (writing reset and enable)
• it does not use SystemC utilities which make coding easier

Best regards

[veeresh k]

Ok Eyck.

Thanx for d reply . ?

It wont be clear untill n unless,i do more n more examples on my own.

To certain extent, u guys made me clear of few topics.

Thank you once again.