Parameters and parameterized port widths in IPXACT 1685-2009

[am91]

Hi,

I am using the IPXACT 2009 standard to describe a verilog module. The module has a bunch of parameters and ports whose width depends on these parameters. I had a couple of questions regarding this:

 

1) Do the parameters go under "<spirit:model>..<spirit:modelParameters>" or under ""<spirit:model><spirit:views><spirit:view><spirit:parameters>" ?

2) From what I understand, there seems to be way to describe variable width ports in the 2014 standard but not in the 2009 standard?

 

Thanks.

[kock]

Hello,

ad 1) The Verilog module parameters should be described as modelParameters in IP-XACT 2009. In IP-XACT 2014, modelParameters are renamed into moduleParameters located in componentInstantiation.

ad 2) Variable width ports can be described in IP-XACT 2009 and 2014. In IP-XACT 2009, the left and right values of port vector are described in XPATH expressions. In IP-XACT 2014, the expression language has been changed to SystemVerilog. You can express left and right values as SystemVerilog expression in the component parameters. You should also make the Verilog moduleParameters in the componentInstantiations expressions in terms of component parameters because it is not allowed to use componentInstantiation specific parameters outside of the componentInstantiation scope (in this case left and right). If you apply the XST transform on an IP-XACT 2009 component with modelParameters to generate the IP-XACT 2014 version of that component, you will see how component parameters are used set moduleParameters.

Best regards,
Erwin

[am91]

11 hours ago, kock said:

be described as modelParameters in IP-XACT 2009. In IP-XACT 2014, modelParameters are renamed into moduleParameters located in componentInstantiation.

ad 2) Variable width ports can be described in IP-

Hi Erwin,

Thanks for the quick response! Could you please elaborate a little more on "In IP-XACT 2009, the left and right values of port vector are described in XPATH expressions" ? I am not sure how I could use this to cover all parameterized and non parameretized verilog expressions (that could be used to define the port widths).

 

Thanks.

[kock]

Hi,
Here is an example:

Verilog module:
module my_module(my_port);
parameter my_parameter = 12;
input wire [my_parameter:0] my_port;
endmodule

And the a corresponding IP-XACT 2009 description:
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
  <spirit:vendor>Vendor</spirit:vendor>
  <spirit:library>Library</spirit:library>
  <spirit:name>my_module</spirit:name>
  <spirit:version>1.0</spirit:version>
  <spirit:model>
    <spirit:views>
      <spirit:view>
        <spirit:name>import</spirit:name>
        <spirit:envIdentifier>::</spirit:envIdentifier>
        <spirit:language>verilog</spirit:language>
        <spirit:modelName>my_module</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>VerilogSource</spirit:localName>
        </spirit:fileSetRef>
      </spirit:view>
    </spirit:views>
    <spirit:ports>
      <spirit:port>
        <spirit:name>my_port</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:resolve="dependent" spirit:id="my_port_LEFT_id" spirit:dependency="id('my_parameter')">12</spirit:left>
            <spirit:right>0</spirit:right>
          </spirit:vector>
        </spirit:wire>
      </spirit:port>
    </spirit:ports>
    <spirit:modelParameters>
      <spirit:modelParameter>
        <spirit:name>my_parameter</spirit:name>
        <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="my_parameter">12</spirit:value>
      </spirit:modelParameter>
    </spirit:modelParameters>
  </spirit:model>
  <spirit:fileSets>
    <spirit:fileSet>
      <spirit:name>VerilogSource</spirit:name>
      <spirit:file>
        <spirit:name>my_module.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
    </spirit:fileSet>
  </spirit:fileSets>
</spirit:component>

The attribute value in spirit:dependency="id('my_parameter')" is an XPATH expression in terms of the modelParameter. The evaluated value of this expression determines the actual value of left value of the port. The given value 12 is a default value similar to the default value in the Verilog module.

In this way, you can describe all your Verilog parameters as IP-XACT component parameters or modelParameters. You need to translate the Verilog expressions that calculate the port width to XPATH expressions in IP-XACT 2009. As mentioned, this is not needed anymore in IP-XACT 2014.

Best regards,
Erwin