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Referencing the memoryMap of a sub-component


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I am working on a project where we have multiple independent IP designs which i'll call "cores".  Each core has its own set of registers accessed through a single register interface bus.  We also have subsystems which have some top level registers and instantiate multiple cores (sometimes multiple instances of the same core).  There is still a single register interface bus which is used to access all of the cores (each is instantiated with an base address offset such that none of there addresses overlap with other cores).

Each Core has a corresponding IP-Xact component description which defines the basic memoryMaps for that core. Basically the XML file consists of only the VLNV and the memoryMaps section.  So far this has worked fine for our needs at the core level.  However I'm not sure how to define the overall memoryMap of a subsystem consisting of multiple cores.

My understanding is that I need to make a component for the subsystem which defines its own top level registers in its memoryMaps section, however I don't see how I can reference the maps of other components within the subsystems' memory map.


My question would be:

 How can I define the memoryMap of the subsystem as a whole without having to literally copy the memoryMap of a core into the memoryMap of the subsystem.

Is there a fundemental flaw in the way I am thinking about this?


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A global system memory map can be computed. The component for which a global memory map is computed should have a master bus interface referencing an address space. The global memory map will then be computed in the address space by locating the peripheral component memory maps in that address space. The set of reachable peripherals is determined by interconnections between bus interfaces of component instances and the internal component bridges and channels. The addresses as seen by the master component are calculated along the paths from peripheral component instances to master component instances. Perhaps it helps to read the IP-XACT user guide available via http://www.accellera.org/images/downloads/standards/ip-xact/IP-XACT_User_Guide_2018-02-16.pdf

The computed global memory map can be written out as a single IP-XACT component memory map. This is typically an automated process and not done manually indeed.


Best regards,



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  • 5 months later...

Hi Erwin,

Thank you for the info. I've been reading through the User Guide and it doesn't seem to provide all the info I need to do this. For example, in section 3.1.6 it says:


Global memory maps are not described explicitly. Rather, they are computed from the design topology by positioning a memoryMap in addressSpaces.

Yet, it doesn't explain how to put a memoryMap in an addressSpace. You can only put segments in addressSpaces, not memoryMaps.

On 3/29/2018 at 1:55 AM, kock said:

The computed global memory map can be written out as a single IP-XACT component memory map.

Can you please provide an example of what that would look like?



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Hi David,

Let''s create a simple example.

  • Assume some peripheral P with slave interface P_S that references a memory map P_S_M containing an address block P_S_M_B with base address P_S_M_B_base.
  • Assume some bus B with a slave interface B_S and master interface B_M. The master interface references an address space B_M_A and has a base address B_M_A_base. The slave interface references a memory map B_S_M containing a subspace map B_S_M_S. That subspace map references master interface B_M.
  • Assume some cpu C with a master interface C_M that references an address space C_M_A and has base address C_M_A_base.
  • Assume connectivity between the bus interfaces as follows: C_M -> B_S, B_M -> P_S.

First, because of the connection B_M -> P_S, the memory map P_S_M is mapped into address space B_M_A. The address block base address P_S_M_B_base shifts that block in that address space. If the block range does not fit in the address space range it should be clipped.

Second, because of the internal connectivity in the bus by means of the subspace map B_S_M_S, address space B_M_A is mapped into memory map B_S_M. The bus interface base address shifts the address space in the memory map.

Finally, because of the connection C_M -> B_S, the memory map B_S_M is mapped into address space C_M_A. Typically base address C_M_A_base has value 0, or the referenced address space is mapped again in another memory map in which the base address may differ from 0.

In this example the subspace map base address is 0 which is equivalent to creating a transparent bridge rather than a subspace map. The subspace map base address can be used to shift address space further in a memory map. In this case the bridge is called opague, although this term is not used anymore in IEEE 1685-2014. Also I have assumed that all addressing units are identical.

I hope this helps.

Best regards,

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