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SystemC for Hardware Design


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We use SystemC to define specific Hardware Blocks like Memory, Caches and Bus etc. We define Header and CPP files and Include processes to define the functionalities being done by each module. BUT let's say Now we have to define the general settings of the Whole Network (like NEURAL NETWORKS AND DEEP LEARNING NETWORKS) which include Two or three STRUCTS about configuration and we make additional Header and CPP file for this. WILL THAT BE CONSIDER AS A FURTHER HARDWARE IN THE SYSTEM C Design. Is that allowed or not ? This is a general question? Please explain me this in detail? Thanks

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I think you have a misconception about SystemC. It is just a library on top of the C++ language, which helps you to describe the structure and behaviour of your hardware and software system. What will be considered as hardware and what as software depends on the language elements you use: An SC_MODULE with ports will or sockets will be considered as hardware due to the semantics associated to the used classes. A header or CPP file as well as as generic functions, classes, or structs do not have any particular semantic attached to it, which would qualify them from the beginning as hardware. They only have the semantics, which are imposed by the ISO C++ standard.

Grouping parameters describing different aspects of your systems in structs is a good approach. I use it for any module, which has several parameters, which interdepend from each other. I usually default initialise all members to form a sensible parameter set. The user then may alter these parameters before passing the whole struct as argument to the module's constructor. It is in the constructor, where I do consistency checks between the parameters to ensure that the module gets properly configured. If you have different sets of parameters for different use cases of your module (e.g., system-level parameters during the top-down design phase and back-annotated device-level data for bottom-up verification), they can be grouped into separate structs. Overload-resolution can then automatically choose the appropriate constructor, which derives internal secondary parameters, which are then actually used in the behavioural description of your module. To describe properties of whole systems, you may group these module parameter structs into bigger structures, to pass a single struct to your top-level module.

To get better tooling support, you may consider to have a look to the SystemC CCI standard, which is currently in the public review phase:

Though, I think it is a good idea that you get first familiar with C++ itself and the foundations of SystemC before continuing to model a complex system. A good book on SystemC is, e.g., "SystemC from the Ground Up" by David C. Black, Jack Donovan, et al.

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For synthesizable SystemC, there is a standard, but even so it is VERY vendor/software dependent. So the answers for using SystemC in a synthesizable context depend on which synthesis software you intend to use. Several companies often software for this (including, but no limited to, Cadence, Xilinx, Mentor (now Siemens)). In general, my experience is that most C/C++ is synthesizable subject to some simple restrictions (e.g. may not use the heap (i.e. new/delete/malloc/free), which also often means you will not be able to use very much of the STL, which is heavily dynamic. Polymorphism is restricted if not forbidden by most of the tools as well. That said, I have successfully synthesized huge designs fairly easily and with decent results.

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