Questasim_10.0a error loading design

[minhmend]

Hi,

I have been using Questasim_10.0a for a while but recently it has a error "Error loading design".

I'm sure that there's no error on my design because I had tried with a very simple module with only input and output declaration. The problem is when I re-instal questasim, it can run properly again.

I also tried with other version of questasim (ver 10.1) but it produced the same error after several times running simulation.

vlog -sv -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF D:/Work/test/Top.sv
# QuestaSim vlog 10.0a Compiler 2011.02 Feb 20 2011
# -- Compiling module Top
# 
# Top level modules:
# 	Top
vsim -novopt work.Top
# vsim -novopt work.Top 
[COLOR="Red"]# Error loading design[/COLOR]

I would very appreciate if anyone can help me to fix this error.

Many thanks in advance!

Minh,

[dave_59]

Is this only your design or any example provided with the release that has this problem?

One thing to try is delete your work library and recreate it with "vlib work". You should always do this when switching between major revisions of the simulator.

The vlog command line does not need -sv if all SystemVerilog files have the extension *.sv

Try the vsim command line "vsim Top" without the -novopt.

If you have further issues, you need to contact Mentor support. You will also need to provide your OS/platform.