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Project with multiple SystemC Simulations leads to an exception


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In my project there are several functions which perform SystemC simulations (each has its own declaration prelude and sc_start()). So they are constructed as follows:

// first Simulation:
sc_signal<double> s1_sim1;
ControlFoo<double> *cf = new ControlFoo<double>();
sc_start(); // works fine
// second Simulation:
sc_signal<double> s1_sim2; // this leads to an exception

The first simulation runs as desired until the sc_stop(). But when I try to declare new sc_signals after the first simulation is completed then it comes to an exception.

How do I solve my problem?

Best regards



(I also asked this on stackoverflow but no response yet. http://stackoverflow.com/questions/42997196/project-with-multiple-systemc-simulations-leads-to-an-exception)

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SystemC currently does not support to do several distinct simulations from within the same application process. Once elaboration is finished, you cannot instantiate new modules, ports, and channels, as they would modify the design hierarchy. Furthermore, after an sc_stop(), it is an error to call sc_start() again, see IEEE Std 1666-2011, clause 4.5.3: "It shall be an error for the application to call function sc_start after function sc_stop has been called."

You may be able to arrange for your design hierarchy to stay constant across all simulation runs. In that case, you could make changes to the parameterization of the module instances in your hierarchy to modify stimuli and behavior each time an sc_start() hands back control to your sc_main().

If you need to do several simulations with divergent design hierarchies, you will have to launch an own process for each simulation case. You could store the parameters for the different simulation runs in one or more configuration files and pass this config file plus possible additional parameters as command line arguments to your SystemC application to easily switch between the different cases. A script file can then automate the execution of all the different necessary simulations.

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