hrishikeshadn Posted April 19, 2016 Report Posted April 19, 2016 In case of UVM ,config_db can be accessed in any component or object which helps mainly the dynamic creation of component/models.Whether any option is present in SYSTEM C ? Quote
Martin Barnasconi Posted April 19, 2016 Report Posted April 19, 2016 The SystemC class library itself does not support this configuration functionality. The UVM-SystemC class library obviously adds this functionality, since we target exactly the same functionality and features as UVM-SystemVerilog. Quote
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.