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Showing results for tags 'configuration'.
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In case of UVM ,config_db can be accessed in any component or object which helps mainly the dynamic creation of component/models.Whether any option is present in SYSTEM C ?
xua posted a topic in UVM SystemVerilog DiscussionsHi, I am using uvm_resource_db to set and get any component configuration. But I am getting an error saying configuration object is not found. Its something that its not able to get the config object from configuration space. In env build_phase, I do set the configuration as below: uvm_resource_db#(io_config)::set("io_agent_0*","io_agent_config",m_io_config,this); And in io_agent, below code is used to get the configuration: assert(uvm_resource_db#(io_config)::read_by_name(get_full_name(),"io_agent_config",cfg,this) else uvm_report_fatal("io_agent","not able to get the configuration object"); Kindly let me know if there is anything wrong in the above usage. And also, can I do setting configuration through uvm_resource_db and getting it through uvm_config_db. Thanks A.Sunitha