adder - hierarchy- output issue

[meera]

Hi,

 

  i was trying to obtain a fulladder through half adder. i was able to build and run the program but i find that outputs are not as expected. i feel it must be something to do with sensitivity. could anyone pls suggest that the mistake is.

 

full_adder.h

 

#include "half_adder.h"

SC_MODULE (full_adder) {

sc_in<bool>a,b ,cin;

sc_out<bool>sum,carry;

sc_signal<bool> c1,c2,s1;

 

void disp()

{

cout<<"a="<<a<<endl;

cout<<"b="<<b<<endl;

cout<<"cin="<<cin<<endl;

cout<<"sum="<<sum<<endl;

cout<<"carry="<<carry<<endl;

cout<<endl;

}

 

void or()

      {

carry= c1|c2;

}

 

half_adder *halfl_adder1_ptr , *halfl_adder2_ptr;

 

SC_CTOR(full_adder){

 

halfl_adder1_ptr= new and("half_adder1");

halfl_adder1_ptr->a(a);

halfl_adder1_ptr->b(;

halfl_adder1_ptr->sum(s1);

halfl_adder1_ptr->carry(c1);

 

   

halfl_adder2_ptr= new and("half_adder2");

   halfl_adder2_ptr->a(s1);

   halfl_adder2_ptr->b(cin);

   halfl_adder2_ptr->sum(sum);

   halfl_adder2_ptr->carry(c2);

 

SC_METHOD(or);

sensitive <<c2<<c1;

SC_METHOD(disp);

sensitive <<sum<<carry;

  }

~full_adder(){

delete halfl_adder1_ptr;

delete halfl_adder2_ptr;

}

};

 

 

 

 

 

 

 

 

 

[apfitch]

It's hard to say. One obvious issue is that if sum and carry change on different delta cycles, you'll see two printouts,

Alan

[meera]

Hi Alan,

 is there any other keyword instead of sensitive? which could be used, to achieve the desired output .

 

thanks

[apfitch]

I'm not sure what you mean. You could change the printing code to use an SC_THREAD, and then you could add a small wait to allow the outputs to settle. And make the printing process only sensitive to sum, e.g.

#include "half_adder.h"
SC_MODULE (full_adder) {
  sc_in<bool>a,b ,cin;
  sc_out<bool>sum,carry;  
  sc_signal<bool> c1,c2,s1;
 
  void disp()
  {
    while (true) {
      wait(1, SC_NS);
      cout<<"a="<<a<<endl;
      cout<<"b="<<b<<endl;
      cout<<"cin="<<cin<<endl;
      cout<<"sum="<<sum<<endl;
      cout<<"carry="<<carry<<endl;
      cout<<endl;
    }
  }
 ...
 
 
  SC_CTOR(full_adder){
   ...
    SC_THREAD(disp);
    sensitive <<sum;
  }
...
};

regards

Alan

[aixeta]

Hi,

I'm trying to make 8-bit Carry Select Adder that consist of some adder 4 bit with full bit adder. I've tried to make full bit adder and the testbench. It worked very well.

The problem is, when i want to make a 4 adder, i need to split binary into array. The error that i got it was only E529

Error: (E529) insert module failed: simulation running
In file: ../../../src/sysc/kernel/sc_module_registry.cpp:49
In process: ADDER4BIT.do_add4 @ 0 s

The sc_main() is in the add4_tb.cpp with the testbench module.

I believe, i have a problem in the add4.cpp around code below but i'm not sure what it is.

void do_add4(){
  cout<<endl<<"Constructing Adder 4 bit"<<endl;
  sc_lv<4> tmpA = A_s.read();
    A0 = tmpA[0];
    A1 = tmpA[1];
    A2 = tmpA[2];
    A3 = tmpA[3];

    sc_lv<4> tmpB = B_s.read();
    B0 = tmpB[0];
    B1 = tmpB[1];
    B2 = tmpB[2];
    B3 = tmpB[3];
    //Instantiate 4 BIT_ADDERs to make a 4-bit ADDER

    fa adder1("BitAdder1");
    adder1.a(A0);
    adder1.b(B0);
    adder1.cin(CIN_s);
    adder1.sum(S0);
    adder1.cout(cout1);

    ...

Full code attached below.

add4.h

add4_tb.cpp

fa.h

[Roman Popov]

9 hours ago, aixeta said:

The problem is, when i want to make a 4 adder, i need to split binary into array. The error that i got it was only E529

Error: (E529) insert module failed: simulation running
In file: ../../../src/sysc/kernel/sc_module_registry.cpp:49
In process: ADDER4BIT.do_add4 @ 0 s

 

SystemC does not allow to change structure of design during simulation. Modules and other sc_objects like ports and signals could not be created during simulation. 

Check IEEE SystemC standard , Chapter 4: " Elaboration and simulation semantics " for more details.

[aixeta]

Thank you roman, I can understand better about elaboration and simulation from your reference.

I'm realize that i cannot do a port binding from a MEtHOD, THREAD, or CTHREAD. "Port binding" that i mean is to declare a new object module  like example below:

void do_add4(){
  sc_lv<4> tmpA = A_s.read();
  A3 = tmpA[3];
  A2 = tmpA[2];
  A1 = tmpA[1];
  A0 = tmpA[0];

  sc_lv<4> tmpB = B_s.read();
  B3 = tmpB[3];
  B2 = tmpB[2];
  B1 = tmpB[1];
  B0 = tmpB[0];

  fa adder1("adder1"); //This is the problem right?  
  adder1.a(A0);
  adder1.b(B0);
  adder1.carryIn(CIN_s);
  adder1.sum(S0);
  adder1.carryOut(cout1);
}

SC_CTOR(add4){
  cout<<endl<<"Constructing Adder 4 bit"<<endl;
  SC_METHOD(do_add4);		
}

Is my understanding correct?

For instance, if i have a "top" module and i want to bind with (lets say) "A" module, then "A" module should be binded/connected with "B" module. Is there any way to do the binding between "A" module and "B" module? Because i don't have any problem if that only from "top" module to "A" module, but i cannot do the binding between A and B.

I want to try to do pin level code in systemC. In verilog i can do the binding like the example code below

module A(
A,
B,
C,
S,
CO);
input[3:0] A;
input[3:0] B;
input CI;

output CO;
output[3:0] S;
wire [2:0] C;

B b1(A[0],B[0],CI,S[0],C[0]);
B b2(A[1],B[1],C[0],S[1],C[1]);
B b3(A[2],B[2],C[1],S[2],C[2]);
B b4(A[3],B[3],C[2],S[3],CO);

endmodule

Is there any way to do like those code in systemc?

[Roman Popov]

2 hours ago, aixeta said:

Is there any way to do like those code in systemc?

Yes. Read about signals and ports. You just trying use brute-force instead of learning before doing.

 

 

[aixeta]

Hi Roman,

I'm sorry, yes I'm new here in systemC. I had read about it from doulos and asic-world, but i have not found any explanation and example about signal and port for 2 or more derived module. Do you mind give me the simple example about it?

I'm using SystemC 2.3.2 right now.

Thank you.

[Roman Popov]

1 hour ago, aixeta said:

Hi Roman,

I'm sorry, yes I'm new here in systemC. I had read about it from doulos and asic-world, but i have not found any explanation and example about signal and port for 2 or more derived module. Do you mind give me the simple example about it?

I'm using SystemC 2.3.2 right now.

Thank you.

Duolos website definetely has examples with mode than two modules or more than two signals: https://www.doulos.com/knowhow/systemc/tutorial/modules_and_processes/

 

What do you mean by "derived module" ?  Word "derived" in C++ and SystemC is used in a context of OOP, i.e. class can be derived from one or more base classes.