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  1. Hi Roman, I'm sorry, yes I'm new here in systemC. I had read about it from doulos and asic-world, but i have not found any explanation and example about signal and port for 2 or more derived module. Do you mind give me the simple example about it? I'm using SystemC 2.3.2 right now. Thank you.
  2. Thank you roman, I can understand better about elaboration and simulation from your reference. I'm realize that i cannot do a port binding from a MEtHOD, THREAD, or CTHREAD. "Port binding" that i mean is to declare a new object module like example below: void do_add4(){ sc_lv<4> tmpA = A_s.read(); A3 = tmpA[3]; A2 = tmpA[2]; A1 = tmpA[1]; A0 = tmpA[0]; sc_lv<4> tmpB = B_s.read(); B3 = tmpB[3]; B2 = tmpB[2]; B1 = tmpB[1]; B0 = tmpB[0]; fa adder1("adder1"); //This is the problem right? adder1.a(A0); adder1.b(B0); adder1.carryIn(CIN_s); adde
  3. Hi, I'm trying to make 8-bit Carry Select Adder that consist of some adder 4 bit with full bit adder. I've tried to make full bit adder and the testbench. It worked very well. The problem is, when i want to make a 4 adder, i need to split binary into array. The error that i got it was only E529 Error: (E529) insert module failed: simulation running In file: ../../../src/sysc/kernel/sc_module_registry.cpp:49 In process: ADDER4BIT.do_add4 @ 0 s The sc_main() is in the add4_tb.cpp with the testbench module. I believe, i have a problem in the add4.cpp around code below but i'
  4. Thank you sir @StS, It worked. I can install the scv and run the example. Looking foward for the SCV upcoming release.
  5. Hi there, I have an exact same problem with Sephan, when i ran "make' command after do the config the error said like "error: cannot convert 'sc_dt::sc_bv_base::value_type {aka bool}' to 'sc_dt::sc_logic_value_t' in return { this->initialize(); return this->_get_instance()->get_bit(i); } \" I'm using centOS 7 3.10.0-693.5.2.el7.x86_64 and GCC Version gcc version 4.8.5 20150623 (Red Hat 4.8.5-16) (GCC) The scv that i used was "scv-2.0.0a-20161019 " Do you have any suggestion? here the full output making all in sis make[4]: Enterin
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