Jump to content

Recommended Posts

Posted

hi,

 iam new to systemc, i tried programming AND but was felt with port binding issue. could anyone pls tell me where i have gone wrong...

 

 and.h

#include "systemc.h"
 
SC_MODULE(and)
{
sc_in< sc_uint<1> > a, b;
 
sc_out< sc_uint<1> > s;
void my_and()
{
s.write(a.read() & b.read());
cout<<s<<endl;
 }
 
SC_CTOR(and){
SC_METHOD(my_and);
sensitive << a << b;
}
};
 
 
 
and.cpp
 
 
#include "and.h"
 
int sc_main(int argc, char* argv[])
 
{
sc_signal<sc_uint<1> > a,b;
     sc_signal<sc_uint<1> >   s;
and d1("and");
 
d1.a(a);
d1.b(B);
d1.s(s);
 
sc_start();
return 0;
}

 

Posted

 

hi,

 iam new to systemc, i tried programming AND but was felt with port binding issue. could anyone pls tell me where i have gone wrong...

 

 and.h

#include "systemc.h"
 
SC_MODULE(and)
{
sc_in< sc_uint<1> > a, b;
 
sc_out< sc_uint<1> > s;
void my_and()
{
s.write(a.read() & b.read());
cout<<s<<endl;
 }
 
SC_CTOR(and){
SC_METHOD(my_and);
sensitive << a << b;
}
};
 
 
 
and.cpp
 
 
#include "and.h"
 
int sc_main(int argc, char* argv[])
 
{
sc_signal<sc_uint<1> > a,b;
     sc_signal<sc_uint<1> >   s;
and d1("and");
 
d1.a(a);
d1.b(cool.png;
d1.s(s);
 
sc_start();
return 0;
}

Hello,

Please provide the error message.

 

In your SC_MOULE declaration/definition for the 'and' gate,

have you tried:

 

sc_in< sc_uint<1> > a;

sc_in< sc_uint<1> > b;

 

Instead of(as you have rioght now):

sc_in< sc_uint<1> > a, b;

 

 

In your "int sc_main" I am afraid you do not 

insert any values into your signal lines for

the 'and' module to operate on.

 

Finally, please check out some new book on

SystemC -- unfortunately the material available

on some Web sites is hopelessly outdated, with

the authors being too lazy to update them.

 

Hope this helps.

Posted

hi,

 thanks for replying . well iam now not getting any error messages (for the program)but as you said i havent inserted values in sc_main, can you pls elaborate on that point as to how to do that , is it not possible to assign values in cmd.exe window? iam using visual studio 2012. as one of the member has pointed out i tried separating the lines, but it didnt help.

Posted

Hi Meera,

  sorry I don't understand your question. But you can assign values to variables in sc_main like you did earlier, i.e.

d1.a(a);
d1.b(;
d1.s(s);
a=1;
b=1;
sc_start(20,SC_NS);
return 0;
}

But if you don't want to write a separate stimulus module, then you probably want to assign more values, i.e.

  a=1;
  b=1;
  sc_start(20,SC_NS);
  a = 0;
  sc_start(20,SC_NS);
  b = 0;
  sc_start(20, SC_NS);
  a = 1;
  sc_start(20, SC_NS);
  return 0;
}

regards

Alan

Posted

hi Alan,

    i got your point, and have added to my program the lines you have suggested but still am not able get the output. I think iam missing something in my program that should call the operation "s" to perform. Could pls go through the program ? and suggest as to what can be done.

 
#include "systemc.h"
 
SC_MODULE(and) {
 
 
  sc_in<sc_uint <1> >a;
  sc_in<sc_uint <1> >b;
  sc_out<sc_uint <2> >s;
 
void my_and() {
 
 
s.write( a.read() | b.read());
cout<<a<<endl;
cout<<b<<endl;
cout<<s<<endl;
             }
SC_CTOR(and){
SC_THREAD(my_and);
 
sensitive << a <<b;
 
        }
 
};
 
 
#include "systemc.h"
#include "and.h"
 
int sc_main(int argc, char* argv[])
 
{
 
sc_signal<sc_uint <1> > a ;
sc_signal<sc_uint <1> > b ;
    sc_signal<sc_uint <2> > s ;
 
 
and d1("And");
d1.a(a);
d1.b(B);
d1.s(s);
a=1;
b=1;
sc_start(20,SC_NS);
  a = 0;
  sc_start(20,SC_NS);
  b = 0;
  sc_start(20, SC_NS);
  a = 1;
  sc_start(20, SC_NS);
  return 0;
}
 
 
  
thank you
Posted

Hi Meera,

 it works for me...

#include "systemc.h"

SC_MODULE(And) {


    sc_in<sc_uint <1> >a;
    sc_in<sc_uint <1> >b;
    sc_out<sc_uint <2> >s;

    void my_and() {
        s.write( a.read() | b.read());
        cout<<a<<endl;
        cout<<b<<endl;
        cout<<s<<endl;
    }

    SC_CTOR(And){
    SC_METHOD(my_and);

    sensitive << a <<b;

    }

};


#include "systemc.h"

int sc_main(int argc, char* argv[])
{

    sc_signal<sc_uint <1> > a ;
    sc_signal<sc_uint <1> > b ;
    sc_signal<sc_uint <2> > s ;


    And d1("And");
    d1.a(a);
    d1.b(;
    d1.s(s);
    a=1;
    b=1;
    sc_start(20,SC_NS);
    a = 0;
    sc_start(20,SC_NS);
    b = 0;
    sc_start(20, SC_NS);
    a = 1;
    sc_start(20, SC_NS);
    return 0;
}

Result

1
1
0
0
1
1
0
0
1
1
0
0

Of course it does an | as you'd changed it from an &

Posted

hi Alan,

 iam getting the same output , but dont you think of the first set when a=1b=1 you are getting s=0 ? what i feel is that for current combination of a,b the result for s is seen in next step. Pls correct me if iam wrong.

 

thanks

Posted

Hello,

Please change the template to "bool" from "sc_uint".  Compile and try. Will work.

 Hi,

i did try doing that , but as i pointed out i feel result of "s" is seen only in the next cycle...what should i do for that?

Posted

 Hi,

i did try doing that , but as i pointed out i feel result of "s" is seen only in the next cycle...what should i do for that?

 

Hello,

I am not sure at all what exactly you mean by "cycle". Please note that the AND operation is a 

pure combinational logic operation, and has nothing to do with any clock. That is why, when

combinational logic circuits are simulated, some values are added to the signal lines, and the

simulation is run for fixed time period, independent of the combinational logic circuit -- no clock

synchronization is required. Please be very clear about what you are doing or trying to achieve.

Posted

hi,

if u execute is u will get to know what iam trying to say as .cpp 

#include "systemc.h"
#include "and.h"
 
int sc_main(int argc, char* argv[])
{
 
    sc_signal<sc_uint <3> > a ;
    sc_signal<sc_uint <3> > b ;
    sc_signal<sc_uint <3> > s ;
 
 
    and d1("And");
    d1.a(a);
    d1.b( B);
    d1.s(s);
    a=3;
b=4;
    sc_start(20,SC_NS);
    a = 1;
b = 2;
    sc_start(20,SC_NS);
a = 3;
    b = 4;
sc_start(20, SC_NS);
    a = 4;
b = 2;
    sc_start(20, SC_NS);
a = 1;
b = 1;
sc_start(20, SC_NS);
    return 0;
}
Posted

Hello,

I am not sure at all what exactly you mean by "cycle". Please note that the AND operation is a 

pure combinational logic operation, and has nothing to do with any clock. That is why, when

combinational logic circuits are simulated, some values are added to the signal lines, and the

simulation is run for fixed time period, independent of the combinational logic circuit -- no clock

synchronization is required. Please be very clear about what you are doing or trying to achieve.

sorry yes u r correct. but if you could execute the lines in my recent post probably you might understand what iam trying to say.

Posted

Hi Meera,

   signals update on the following delta, so when you print the value you print the current value, not the value that will be assigned when the process suspends.

 

The simplest way to make your code print out the final values of the signals would be to put the $display in a separate SC_METHOD, sensitive to s,

 

regards

Alan

 

Edit: oops too much SystemVerilog - I meant cout of course :-)

Posted

Hi Meera,

   signals update on the following delta, so when you print the value you print the current value, not the value that will be assigned when the process suspends.

 

The simplest way to make your code print out the final values of the signals would be to put the $display in a separate SC_METHOD, sensitive to s,

 

regards

Alan

Hi Alan,

   Now iam able to see the correct output. Thanks for  helping me out with the issues.

 

thank you

Meera

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...