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problem with tb of fir filter


A.Elgogary

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i was tring to do an online training by fortedesign on youtube and tried to use the same code but after running got nothing, i think the testbench doesn't run at all ? also i got error from eclispe with any sc_signal < bool > ? 

 

fir.h



 #include <iostream>
 #include "systemc.h"


 SC_MODULE( fir ){

	 sc_in < bool > clk;
	 sc_in < bool> rst;
	 sc_in< sc_int<16> > inp;
	 sc_in < bool > inp_vld;
	 sc_out < bool > inp_rdy;
	 sc_out< sc_int<16> > outp;
	 sc_out< bool> outp_vld;
	 sc_in < bool> outp_rdy;
	 	 void fir_main();

	 SC_CTOR( fir ){

		 SC_CTHREAD( fir_main, clk.pos());
		 reset_signal_is( rst, true);


	 };


 };






fir.cc


 #include "fir.h"
 
 	 const sc_uint< 16 > coef[5] =  {18,77,107,77,18};



void fir::fir_main(){

	cout << "fir_main oper" << endl;

	sc_uint< 16 > taps[5];

	//rest is wrote here till first wait

	for (int i = 4; i > 0; i--) {

		taps[i] = 0;

	}
	//intailaize handscack
	inp_rdy.write(0);
	outp_vld.write(0);
	outp.write( 0 );

	wait();

	while(true){


		sc_int < 16 > in_val;
		sc_int < 16 > out_val;

		inp_rdy.write(1);
		do{
			wait();
		}while(!inp_vld.read());

		in_val = inp.read();
		inp_rdy.write(0);
		//read input into shift register
		for (int i = 4; i > 0; i--) {

			taps[i] = taps[i-1];

		}

			taps[0] = in_val;


			// perfom multiplay and accumulate
			for (int i = 0; i < 5; i++) {

				out_val += coef[i]*taps[i];


			}
			outp_vld.write(1);
			outp.write(out_val);
			do{wait();
			}while(!outp_rdy.read());
			outp_vld.write(0);

		wait();

	}//while


}

tb.h



	#include "systemc.h"
	#include <iostream>


	SC_MODULE (tb){

		 sc_in < bool > clk;
		 sc_out < bool > rst;
		 sc_out< sc_int<16> > inp;
		 sc_out < bool   > inp_vld;
		 sc_in < bool  > inp_rdy;
		 sc_in< sc_int<16> > outp;
		 sc_in< bool  > outp_vld;
		 sc_out < bool > outp_rdy;
		 sc_time starttime[64],endtime[64], clockperiod;

		void source();
		void sink();
		FILE *outfp = NULL;

		SC_CTOR(tb){

			SC_CTHREAD ( source, clk.pos());
			SC_CTHREAD ( sink, clk.pos());

		}


	};

tb.cc

#include "tb.h"

	void tb::source() {
		cout << "source" << endl;
		sc_int < 16 > tmp;
		//rest
		inp.write( 0 );
		inp_vld.write(0);
		rst.write( 1 );
		wait();
		rst.write( 0 );
		wait();



		for(int i = 0; i < 64; i++)
		{
			if (i > 23 && i < 29)
				tmp = 256;
			else
				tmp = 0;

			inp_vld.write(1);
			inp.write (tmp);
			starttime[i] = sc_time_stamp();
			do{
			wait();
			}while(!inp_rdy.read());
			inp_vld.write(0);

		}
		//hanging prevent
		wait(10000);
		printf("sim hang stopped by TB \n");
		sc_stop();

}


	void tb::sink() {
		cout << "sink" << endl;
		sc_int <16> datain;
		//clk peroid
		sc_clock *clkp = DCAST<sc_clock*>(clk.get_interface());
		clockperiod = clkp->period();

		//int port

		outp_rdy.write(0);
		double totalcycles = 0;
		//open sim file

		char output_file[256];
		sprintf(output_file, "./output.dat");
		outfp = fopen(output_file, "w");
		if(outfp == NULL ){
			printf("couldn't open output.dat \n");
			exit(0);
		}

		for(int i=0; i < 64; i++)
		{
			outp_rdy.write(1);
			do{wait();
			}while(!outp_vld.read());

			datain = outp.read();
			endtime[i] = sc_time_stamp();
			totalcycles += (endtime[i] - starttime[i]) / clockperiod;
			outp_rdy.write(0);

			fprintf(outfp, "%d\n", (int)datain);
			cout << i << " :\t" << datain.to_double() << endl;

		}

		//latancy
		double throughput = (starttime[63] - starttime[0]) / clockperiod;
		printf("average latancy is %g cycles.\n", (double)(totalcycles/64));
		printf("average throughut is %g cycles/input.\n", (double)(throughput/63));
		//end sim
		sc_stop();
		fclose(outfp);
		cout << "sim stop" << endl;
	}

main.cc



 #include "systemc.h"
 #include "fir.h"
 #include "tb.h"
 //module connecting fir to tb and run sim


 SC_MODULE( systb ){

	 tb  * tb0;
	 fir * fir0;


	 sc_signal < sc_int < 16 > > inp_sig;
	 sc_signal <  bool > inp_sig_vld;
	 sc_signal <  bool > inp_sig_rdy;
	 sc_signal < bool > rst_sig;

 	 sc_signal < sc_int < 16 > >  outp_sig;
 	 sc_signal <  bool > outp_sig_vld;
 	 sc_signal <  bool > outp_sig_rdy;

   	 sc_clock  clk_sig;

 SC_CTOR( systb )

 	 : clk_sig ("clk_sig", 10, SC_NS)
 	 {

	 cout << "constructor" << endl;

	 tb0 = new tb("tb0");

	 tb0->clk( clk_sig );
	 tb0->rst( rst_sig );
	 tb0->inp( inp_sig );
	 tb0->inp_vld( inp_sig_vld );
	 tb0->inp_rdy( inp_sig_rdy );
	 tb0->outp( outp_sig );
	 tb0->outp_vld( outp_sig_vld );
	 tb0->outp_rdy( outp_sig_rdy );

	 fir0 = new fir("fir0");

	 fir0->clk( clk_sig );
	 fir0->rst( rst_sig );
	 fir0->inp( inp_sig );
	 fir0->inp_vld( inp_sig_vld );
	 fir0->inp_rdy( inp_sig_rdy );
	 fir0->outp( outp_sig );
	 fir0->outp_vld( outp_sig_vld );
	 fir0->outp_rdy( outp_sig_rdy );

    }


 	 ~systb(){

 		 delete tb0;
 		 delete fir0;
 		cout << "delete" << endl;
 	 }
 };




 systb *top = NULL;

 int sc_main(int, char* [])
 {

	 top = new systb("top");
	 cout << "sim start" << endl;

	 	 sc_trace_file *fp;

	     fp=sc_create_vcd_trace_file("wave");
	     fp->set_time_unit(100, SC_PS);

	     sc_trace(fp,top->clk_sig , "clk_sig");
	     sc_trace(fp,top->rst_sig , "rst_sig");

	      sc_start(200, SC_NS);
	      sc_close_vcd_trace_file(fp);

	 return 0;

 }

also if there is some reference or training to increase my knowledge with systemc would be more than happy .

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yes here is the error i got only with clock but some times with sc_signal < bool > only , also i read online and found there is a bug with eclipse generally with c++ 
 

The type 'sc_core::sc_clock' must implement the inherited pure virtual method 
'sc_core::sc_signal_write_if::write'
- Line breakpoint: main.cc [line: 23]

also other programs run normally and generate waveforms but only this one stucks after simulation start in main func and the call of constructor in systb above without calling tb as i think.
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i was tring to do an online training by fortedesign on youtube and tried to use the same code but after running got nothing, i think the testbench doesn't run at all ? also i got error from eclispe with any sc_signal < bool > ? 

 

fir.h



 #include <iostream>
 #include "systemc.h"


 SC_MODULE( fir ){

	 sc_in < bool > clk;
	 sc_in < bool> rst;
	 sc_in< sc_int<16> > inp;
	 sc_in < bool > inp_vld;
	 sc_out < bool > inp_rdy;
	 sc_out< sc_int<16> > outp;
	 sc_out< bool> outp_vld;
	 sc_in < bool> outp_rdy;
	 	 void fir_main();

	 SC_CTOR( fir ){

		 SC_CTHREAD( fir_main, clk.pos());
		 reset_signal_is( rst, true);


	 };


 };






fir.cc


 #include "fir.h"
 
 	 const sc_uint< 16 > coef[5] =  {18,77,107,77,18};



void fir::fir_main(){

	cout << "fir_main oper" << endl;

	sc_uint< 16 > taps[5];

	//rest is wrote here till first wait

	for (int i = 4; i > 0; i--) {

		taps[i] = 0;

	}
	//intailaize handscack
	inp_rdy.write(0);
	outp_vld.write(0);
	outp.write( 0 );

	wait();

	while(true){


		sc_int < 16 > in_val;
		sc_int < 16 > out_val;

		inp_rdy.write(1);
		do{
			wait();
		}while(!inp_vld.read());

		in_val = inp.read();
		inp_rdy.write(0);
		//read input into shift register
		for (int i = 4; i > 0; i--) {

			taps[i] = taps[i-1];

		}

			taps[0] = in_val;


			// perfom multiplay and accumulate
			for (int i = 0; i < 5; i++) {

				out_val += coef[i]*taps[i];


			}
			outp_vld.write(1);
			outp.write(out_val);
			do{wait();
			}while(!outp_rdy.read());
			outp_vld.write(0);

		wait();

	}//while


}

tb.h



	#include "systemc.h"
	#include <iostream>


	SC_MODULE (tb){

		 sc_in < bool > clk;
		 sc_out < bool > rst;
		 sc_out< sc_int<16> > inp;
		 sc_out < bool   > inp_vld;
		 sc_in < bool  > inp_rdy;
		 sc_in< sc_int<16> > outp;
		 sc_in< bool  > outp_vld;
		 sc_out < bool > outp_rdy;
		 sc_time starttime[64],endtime[64], clockperiod;

		void source();
		void sink();
		FILE *outfp = NULL;

		SC_CTOR(tb){

			SC_CTHREAD ( source, clk.pos());
			SC_CTHREAD ( sink, clk.pos());

		}


	};

tb.cc

#include "tb.h"

	void tb::source() {
		cout << "source" << endl;
		sc_int < 16 > tmp;
		//rest
		inp.write( 0 );
		inp_vld.write(0);
		rst.write( 1 );
		wait();
		rst.write( 0 );
		wait();



		for(int i = 0; i < 64; i++)
		{
			if (i > 23 && i < 29)
				tmp = 256;
			else
				tmp = 0;

			inp_vld.write(1);
			inp.write (tmp);
			starttime[i] = sc_time_stamp();
			do{
			wait();
			}while(!inp_rdy.read());
			inp_vld.write(0);

		}
		//hanging prevent
		wait(10000);
		printf("sim hang stopped by TB \n");
		sc_stop();

}


	void tb::sink() {
		cout << "sink" << endl;
		sc_int <16> datain;
		//clk peroid
		sc_clock *clkp = DCAST<sc_clock*>(clk.get_interface());
		clockperiod = clkp->period();

		//int port

		outp_rdy.write(0);
		double totalcycles = 0;
		//open sim file

		char output_file[256];
		sprintf(output_file, "./output.dat");
		outfp = fopen(output_file, "w");
		if(outfp == NULL ){
			printf("couldn't open output.dat \n");
			exit(0);
		}

		for(int i=0; i < 64; i++)
		{
			outp_rdy.write(1);
			do{wait();
			}while(!outp_vld.read());

			datain = outp.read();
			endtime[i] = sc_time_stamp();
			totalcycles += (endtime[i] - starttime[i]) / clockperiod;
			outp_rdy.write(0);

			fprintf(outfp, "%d\n", (int)datain);
			cout << i << " :\t" << datain.to_double() << endl;

		}

		//latancy
		double throughput = (starttime[63] - starttime[0]) / clockperiod;
		printf("average latancy is %g cycles.\n", (double)(totalcycles/64));
		printf("average throughut is %g cycles/input.\n", (double)(throughput/63));
		//end sim
		sc_stop();
		fclose(outfp);
		cout << "sim stop" << endl;
	}

main.cc



 #include "systemc.h"
 #include "fir.h"
 #include "tb.h"
 //module connecting fir to tb and run sim


 SC_MODULE( systb ){

	 tb  * tb0;
	 fir * fir0;


	 sc_signal < sc_int < 16 > > inp_sig;
	 sc_signal <  bool > inp_sig_vld;
	 sc_signal <  bool > inp_sig_rdy;
	 sc_signal < bool > rst_sig;

 	 sc_signal < sc_int < 16 > >  outp_sig;
 	 sc_signal <  bool > outp_sig_vld;
 	 sc_signal <  bool > outp_sig_rdy;

   	 sc_clock  clk_sig;

 SC_CTOR( systb )

 	 : clk_sig ("clk_sig", 10, SC_NS)
 	 {

	 cout << "constructor" << endl;

	 tb0 = new tb("tb0");

	 tb0->clk( clk_sig );
	 tb0->rst( rst_sig );
	 tb0->inp( inp_sig );
	 tb0->inp_vld( inp_sig_vld );
	 tb0->inp_rdy( inp_sig_rdy );
	 tb0->outp( outp_sig );
	 tb0->outp_vld( outp_sig_vld );
	 tb0->outp_rdy( outp_sig_rdy );

	 fir0 = new fir("fir0");

	 fir0->clk( clk_sig );
	 fir0->rst( rst_sig );
	 fir0->inp( inp_sig );
	 fir0->inp_vld( inp_sig_vld );
	 fir0->inp_rdy( inp_sig_rdy );
	 fir0->outp( outp_sig );
	 fir0->outp_vld( outp_sig_vld );
	 fir0->outp_rdy( outp_sig_rdy );

    }


 	 ~systb(){

 		 delete tb0;
 		 delete fir0;
 		cout << "delete" << endl;
 	 }
 };




 systb *top = NULL;

 int sc_main(int, char* [])
 {

	 top = new systb("top");
	 cout << "sim start" << endl;

	 	 sc_trace_file *fp;

	     fp=sc_create_vcd_trace_file("wave");
	     fp->set_time_unit(100, SC_PS);

	     sc_trace(fp,top->clk_sig , "clk_sig");
	     sc_trace(fp,top->rst_sig , "rst_sig");

	      sc_start(200, SC_NS);
	      sc_close_vcd_trace_file(fp);

	 return 0;

 }

also if there is some reference or training to increase my knowledge with systemc would be more than happy .

 

Hello,

 As the others have noted, there could be problem with the environment variables. Also, if you

are starting out with SystemC, please try out a simple example, preferably of your own -- e.g.,

a 2 input NAND gate. That way, if there are any issues with the environment variables, these

can be identified quickly. Hope that helps.

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i was tring to do an online training by fortedesign on youtube and tried to use the same code but after running got nothing, i think the testbench doesn't run at all ? also i got error from eclispe with any sc_signal < bool > ? 

 

fir.h



 #include <iostream>
 #include "systemc.h"


 SC_MODULE( fir ){

	 sc_in < bool > clk;
	 sc_in < bool> rst;
	 sc_in< sc_int<16> > inp;
	 sc_in < bool > inp_vld;
	 sc_out < bool > inp_rdy;
	 sc_out< sc_int<16> > outp;
	 sc_out< bool> outp_vld;
	 sc_in < bool> outp_rdy;
	 	 void fir_main();

	 SC_CTOR( fir ){

		 SC_CTHREAD( fir_main, clk.pos());
		 reset_signal_is( rst, true);


	 };


 };






fir.cc


 #include "fir.h"
 
 	 const sc_uint< 16 > coef[5] =  {18,77,107,77,18};



void fir::fir_main(){

	cout << "fir_main oper" << endl;

	sc_uint< 16 > taps[5];

	//rest is wrote here till first wait

	for (int i = 4; i > 0; i--) {

		taps[i] = 0;

	}
	//intailaize handscack
	inp_rdy.write(0);
	outp_vld.write(0);
	outp.write( 0 );

	wait();

	while(true){


		sc_int < 16 > in_val;
		sc_int < 16 > out_val;

		inp_rdy.write(1);
		do{
			wait();
		}while(!inp_vld.read());

		in_val = inp.read();
		inp_rdy.write(0);
		//read input into shift register
		for (int i = 4; i > 0; i--) {

			taps[i] = taps[i-1];

		}

			taps[0] = in_val;


			// perfom multiplay and accumulate
			for (int i = 0; i < 5; i++) {

				out_val += coef[i]*taps[i];


			}
			outp_vld.write(1);
			outp.write(out_val);
			do{wait();
			}while(!outp_rdy.read());
			outp_vld.write(0);

		wait();

	}//while


}

tb.h



	#include "systemc.h"
	#include <iostream>


	SC_MODULE (tb){

		 sc_in < bool > clk;
		 sc_out < bool > rst;
		 sc_out< sc_int<16> > inp;
		 sc_out < bool   > inp_vld;
		 sc_in < bool  > inp_rdy;
		 sc_in< sc_int<16> > outp;
		 sc_in< bool  > outp_vld;
		 sc_out < bool > outp_rdy;
		 sc_time starttime[64],endtime[64], clockperiod;

		void source();
		void sink();
		FILE *outfp = NULL;

		SC_CTOR(tb){

			SC_CTHREAD ( source, clk.pos());
			SC_CTHREAD ( sink, clk.pos());

		}


	};

tb.cc

#include "tb.h"

	void tb::source() {
		cout << "source" << endl;
		sc_int < 16 > tmp;
		//rest
		inp.write( 0 );
		inp_vld.write(0);
		rst.write( 1 );
		wait();
		rst.write( 0 );
		wait();



		for(int i = 0; i < 64; i++)
		{
			if (i > 23 && i < 29)
				tmp = 256;
			else
				tmp = 0;

			inp_vld.write(1);
			inp.write (tmp);
			starttime[i] = sc_time_stamp();
			do{
			wait();
			}while(!inp_rdy.read());
			inp_vld.write(0);

		}
		//hanging prevent
		wait(10000);
		printf("sim hang stopped by TB \n");
		sc_stop();

}


	void tb::sink() {
		cout << "sink" << endl;
		sc_int <16> datain;
		//clk peroid
		sc_clock *clkp = DCAST<sc_clock*>(clk.get_interface());
		clockperiod = clkp->period();

		//int port

		outp_rdy.write(0);
		double totalcycles = 0;
		//open sim file

		char output_file[256];
		sprintf(output_file, "./output.dat");
		outfp = fopen(output_file, "w");
		if(outfp == NULL ){
			printf("couldn't open output.dat \n");
			exit(0);
		}

		for(int i=0; i < 64; i++)
		{
			outp_rdy.write(1);
			do{wait();
			}while(!outp_vld.read());

			datain = outp.read();
			endtime[i] = sc_time_stamp();
			totalcycles += (endtime[i] - starttime[i]) / clockperiod;
			outp_rdy.write(0);

			fprintf(outfp, "%d\n", (int)datain);
			cout << i << " :\t" << datain.to_double() << endl;

		}

		//latancy
		double throughput = (starttime[63] - starttime[0]) / clockperiod;
		printf("average latancy is %g cycles.\n", (double)(totalcycles/64));
		printf("average throughut is %g cycles/input.\n", (double)(throughput/63));
		//end sim
		sc_stop();
		fclose(outfp);
		cout << "sim stop" << endl;
	}

main.cc



 #include "systemc.h"
 #include "fir.h"
 #include "tb.h"
 //module connecting fir to tb and run sim


 SC_MODULE( systb ){

	 tb  * tb0;
	 fir * fir0;


	 sc_signal < sc_int < 16 > > inp_sig;
	 sc_signal <  bool > inp_sig_vld;
	 sc_signal <  bool > inp_sig_rdy;
	 sc_signal < bool > rst_sig;

 	 sc_signal < sc_int < 16 > >  outp_sig;
 	 sc_signal <  bool > outp_sig_vld;
 	 sc_signal <  bool > outp_sig_rdy;

   	 sc_clock  clk_sig;

 SC_CTOR( systb )

 	 : clk_sig ("clk_sig", 10, SC_NS)
 	 {

	 cout << "constructor" << endl;

	 tb0 = new tb("tb0");

	 tb0->clk( clk_sig );
	 tb0->rst( rst_sig );
	 tb0->inp( inp_sig );
	 tb0->inp_vld( inp_sig_vld );
	 tb0->inp_rdy( inp_sig_rdy );
	 tb0->outp( outp_sig );
	 tb0->outp_vld( outp_sig_vld );
	 tb0->outp_rdy( outp_sig_rdy );

	 fir0 = new fir("fir0");

	 fir0->clk( clk_sig );
	 fir0->rst( rst_sig );
	 fir0->inp( inp_sig );
	 fir0->inp_vld( inp_sig_vld );
	 fir0->inp_rdy( inp_sig_rdy );
	 fir0->outp( outp_sig );
	 fir0->outp_vld( outp_sig_vld );
	 fir0->outp_rdy( outp_sig_rdy );

    }


 	 ~systb(){

 		 delete tb0;
 		 delete fir0;
 		cout << "delete" << endl;
 	 }
 };




 systb *top = NULL;

 int sc_main(int, char* [])
 {

	 top = new systb("top");
	 cout << "sim start" << endl;

	 	 sc_trace_file *fp;

	     fp=sc_create_vcd_trace_file("wave");
	     fp->set_time_unit(100, SC_PS);

	     sc_trace(fp,top->clk_sig , "clk_sig");
	     sc_trace(fp,top->rst_sig , "rst_sig");

	      sc_start(200, SC_NS);
	      sc_close_vcd_trace_file(fp);

	 return 0;

 }

also if there is some reference or training to increase my knowledge with systemc would be more than happy .

 

Hello,

I am very curious to know how a Youtube application can communicate with a host computer

that too have a C++/SystemC compiler running on that computer. Any ideas ?

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