constraining data items

[jao16]

Hello

i am extending uvm_sequence_item to define new random data items which will be used to drive the stimulii to the dut. An example being

class cmif_seq_data_item extends uvm_sequence_item;

`uvm_object_utils(cmif_seq_data_item)

// Generate the host Read/Write transactions

// randomly.

rand bit [31:0] host_wdata;

rand bit [3:0] host_wmask ;

rand bit [18:0] host_addr;

rand bit host_adr_val;

rand bit host_rd_n_wr;

endclass;

Now the host_addr and host_wmask items need to be constrained.

host_addr is always word aligned, so i have used

constraint c2 {host_addr[1:0] == 2'b00;}

Now host_wmask can only take on certain values, for example [0,1,3,7,8 ...] etc

To constraint it, i have used

constraint c1 {host_wmask inside {4'b0000, 4'b0001,

4'b0011, 4'b0111,

4'b1000, 4'b1001,

4'b1011, 4'b1100,

4'b1101, 4'b1110};

}

QS: I don't know if the format for constraint c2 is correct or not.

I looked in the 1.1 UVM Users guide and could not find the format for the constraint command to specify valid ranges.

I also looked in the UVM Class reference manual 1.0 and could not find the format for the constraint command.

QS: Apart form the user guide and the class reference manual is there any other guides/reference/books etc which details the syntax of commands like constraint?

Thanks in advance

JO

[bhunter1972]

You won't find this information in the UVM Reference Manual because constraints are all part of the SystemVerilog language. See the LRM 1800-2009 for details on constraints.

Meantime, your constraints look fine to me.

[aji.cvc]

UVM is on top of SystemVerilog language. You need to refer to manuals that come along with tools, online tutorials and books. You may also take up professional training, in case you live in Bangalore, India see www.cvcblr.com/trainings or direct link to our course http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf

BTW - you constraint seems OK (though didn't compile etc.).

Good luck

Ajeetha, CVC

www.cvcblr.com/blog