UVM components in VMM enviroments.

[knoecksj]

What solutions are available for integrating UVM components into existing VMM testbenches? I've seen the VMM/UVM Interoperability Kit on VMMCentral but I have not been able to get any more information about it. It seems like there would be at least a few organizations that have a need for something like this as they migrate from VMM to UVM. Is everybody just rolling their own home grown solutions?

[jadec]

You can download the original OVM-VMM interoperability kit from Accellera:

http://www.accellera.org/activities/vip/ovm_vmm_interop_1_0.tgz

You might ask you simulator support for information on UVM updates to this as well.

[Roman]

Here is the example.

Pls make sure you are using the synopsys-vcs-/E-2011.03-3. The kit in this version is UVM1.0 based.

`include "uvm_vmm_pkg.sv" // The UVM and VMM libraries

import uvm_pkg::*;

import uvi_interop_pkg::*;

typedef uvi_vmm_uvm_env base_env;

`define BASE_NEW_ARG /*no parent arg*/

`define BASE_NEW_CALL /*no parent arg*/

`define PARENT null

`include "hfpb/hfpb_if.sv" // HFPB interface definition

`include "hfpb/clock_reset.sv" // HFPB clock & reset generator

`include "hfpb/hfpb_pkg.sv" // HFPB protocol-specific components

`include "ctypes.sv"

`include "hfpb_components/hfpb_components_pkg.sv" // test-specific

import hfpb_pkg::*;

import hfpb_components_pkg::*;

`include "uvm_macros.svh"

parameter int DATA_SIZE = 8;

parameter int ADDR_SIZE = 9;

// this is the base class for all the tests

typedef hfpb_master_base #(DATA_SIZE, ADDR_SIZE) hfpb_test;

// these are the possible tests we can run. Each is derived

// from hfpb_master_base#()

typedef

hfpb_random_mem_master #(DATA_SIZE, ADDR_SIZE) rand_test;

typedef

hfpb_directed_mem_master #(DATA_SIZE, ADDR_SIZE) directed_test;

//----------------------------------------------------------------------

// Env - this defines our testbench topology.

//----------------------------------------------------------------------

class env #(int DATA_SIZE=8, int ADDR_SIZE=16) extends base_env;

typedef bit [ADDR_SIZE-1:0] addr_t;

hfpb_agent #(DATA_SIZE, ADDR_SIZE) agent;

hfpb_mem #(DATA_SIZE, ADDR_SIZE) mem1;

hfpb_mem #(DATA_SIZE, ADDR_SIZE) mem2;

hfpb_addr_map #(ADDR_SIZE) addr_map;

// can configure with any subtype of 'hfpb_test'

hfpb_test test;

function new(string name `BASE_NEW_ARG);

super.new(name `BASE_NEW_CALL);

addr_map = new();

endfunction

// Build - Set configuration for the HFPB agent, then create it

// and the other testbench components

virtual function void build();

super.build();

// map the lower half of address space to mem1 (slave 0)

// map the upper half of address space to mem2 (slave 1)

addr_map.add_range('h000, 'h0ff, 0);

addr_map.add_range('h100, 'h1ff, 1);

set_config_int("hfpb_agent", "has_monitor", 0);

set_config_int("hfpb_agent", "has_master", 1);

set_config_int("hfpb_agent", "slaves", 2);

set_config_int("hfpb_agent", "has_talker", 0);

set_config_object("*", "addr_map", addr_map, 0);

agent = new("hfpb_agent", `PARENT);

mem1 = new("mem1", `PARENT);

mem2 = new("mem2", `PARENT);

// Ask to build an instance of the base class. Because of

// the override (below), we'll get the test we want.

test = hfpb_test::type_id::create("mem_master", `PARENT);

fork begin

uvm_build();

//if no phase inserted this should push phasing till end of build()

wait(uvm_top.m_current_phase != null);

uvm_top.m_current_phase.wait_for_state(UVM_PHASE_DONE, UVM_EQ);

test.transport_port.connect(agent.transport_export);

mem1.slave_port.connect(agent.slave_export[0]);

mem2.slave_port.connect(agent.slave_export[1]);

end join_none

endfunction

// In VMM-on-top mode, the vmm_env can implement start() and

// wait_for_end() as usual to govern VMM xactor execution.

// By default, in interoperability mode, the vmm_env's

// wait_for_end() will issue an UVM stop_request to end

// the run phase for UVM components. See HTML documentation on

// the avt_uvm_vmm_env wrapper for details.

virtual task wait_for_end();

#0; //needed to avoid scheduling issue

#0 uvm_wait_for_nba_region(); //allow uvm_build to complete

super.wait_for_end();

#0; //needed to avoid scheduling issue

#0 uvm_wait_for_nba_region(); //allow uvm_build to complete

endtask

endclass

//----------------------------------------------------------------------

// Top-Level - Create our env and connect it to the bus interface

// we'll be driving using a virtual interface handle

// contained in a class. Then, specify which test to

// run, this time via a type override in the factory

//----------------------------------------------------------------------

module example_04_IP_integration;

env #(DATA_SIZE, ADDR_SIZE) e;

hfpb_vif #(DATA_SIZE, ADDR_SIZE) hfpb_vif_obj;

clk_rst cr();

clock_reset ck (cr);

hfpb_if #(DATA_SIZE, ADDR_SIZE) bus_if (cr.clk, cr.rst);

initial begin

e = new("env");

hfpb_vif_obj = new(bus_if);

set_config_object("*", "hfpb_vif", hfpb_vif_obj, 0);

// identify the test we want to run by setting

// a factory override.

hfpb_test::type_id::set_type_override(

directed_test::get_type_id());

//OVM2UVM> uvm_enable_print_topology = 1;

//OVM2UVM> FIXME> ovm_root.enable_print_topology = 1; //OVM2UVM>

uvm_default_table_printer.knobs.depth = 2;

fork

ck.run(2,10,0);

join_none

e.run();

$finish();

end

endmodule