qinhailiang 1 Report post Posted July 25, 2011 I downloaded the UVM Run-Time Phases Primer (v0.5.1) from the UVM World Contributions column. ############################################################### When I compiles it under the QuestaSim 10.0b and uvm-1.0p1, the compiler reports waring as follows: vlog -timescale "1ns/1ps" -mfcu -incr -suppress 2181 +acc=rmb -writetoplevels questa.tops +incdir+../../../uvm-1.0p1/src +incdir+../../src ../../../uvm-1.0p1/src/uvm.sv test.sv QuestaSim vlog 10.0b Compiler 2011.05 May 5 2011 -- Compiling package uvm_pkg -- Compiling package uvm_phase_awareness_pkg -- Compiling package blk_a_pkg ** Warning: ../../src/blk_a_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. -- Compiling package blk_b_pkg ** Warning: ../../src/blk_b_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. -- Compiling package rst_pkg -- Compiling package test_pkg -- Compiling package test_a_pkg -- Compiling package test_b_pkg -- Compiling program top Top level modules: top When I simulates it after compiling, the simulator reports errors as follow: # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test -do {do wave.do; run -all; q} -l questa.log -novopt -sv_lib ../../../uvm-1.0p1/lib/uvm_dpi top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_pkg # Loading sv_std.std # Loading work.uvm_pkg # Loading work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_pkg # Loading work.test_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_phase_awareness_pkg # Loading work.uvm_phase_awareness_pkg # Loading work.blk_b_pkg # Loading work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_a_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_a_pkg # Loading work.blk_a_pkg # Loading work.test_a_pkg # Loading work.top # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_a_pkg::backgroundN_seq # Loading .\../../../uvm-1.0p1/lib/uvm_dpi.dll # Error loading design ################################################################# When I compiles it under the QuestaSim 10.0b and uvm-1.1, the compiler reports warings as follows: vlog -timescale "1ns/1ps" -mfcu -incr -suppress 2181 +acc=rmb -writetoplevels questa.tops +incdir+../../../uvm-1.1/src +incdir+../../src ../../../uvm-1.1/src/uvm.sv test.sv QuestaSim vlog 10.0b Compiler 2011.05 May 5 2011 -- Compiling package uvm_pkg -- Compiling package uvm_phase_awareness_pkg -- Compiling package blk_a_pkg ** Warning: ../../src/blk_a_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'start_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check t he spelling of the name 'start_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'finish_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'finish_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'get_sequencer' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please chec k the spelling of the name 'get_sequencer'. -- Compiling package blk_b_pkg ** Warning: ../../src/blk_b_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'start_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check t he spelling of the name 'start_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'finish_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'finish_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'get_sequencer' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please chec k the spelling of the name 'get_sequencer'. -- Compiling package rst_pkg -- Compiling package test_pkg -- Compiling package test_a_pkg -- Compiling package test_b_pkg -- Compiling program top Top level modules: top When I simulates it after compiling, the simulator reports errors as follow: # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test -do {do wave.do; run -all; q} -l questa.log -novopt -sv_lib ../../../uvm-1.1/lib/uvm_dpi top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_pkg # Loading sv_std.std # Loading work.uvm_pkg # Loading work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_pkg # Loading work.test_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_phase_awareness_pkg # Loading work.uvm_phase_awareness_pkg # Loading work.blk_b_pkg # Loading work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_a_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_a_pkg # Loading work.blk_a_pkg # Loading work.test_a_pkg # Loading work.top # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'start_item' in $root.start_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'finish_item' in $root.finish_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'get_sequencer' in $root.get_sequencer. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'start_item' in $root.start_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'finish_item' in $root.finish_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'get_sequencer' in $root.get_sequencer. # Region: /blk_a_pkg::backgroundN_seq # Loading .\../../../uvm-1.1/lib/uvm_dpi.dll # Error loading design # by comparing the source code- uvm-1.0p1 and uvm-1.1-RC5, we find that the differents are in files -uvm_seqence_item and uvm_sequence_base related to the location of create_item, starte_item, finish_item and get_sequencer defined. Please to check it!!!! Thanks!!! Quote Share this post Link to post Share on other sites
mounika 0 Report post Posted September 24, 2019 On 7/25/2011 at 10:36 AM, qinhailiang said: I downloaded the UVM Run-Time Phases Primer (v0.5.1) from the UVM World Contributions column. ############################################################### When I compiles it under the QuestaSim 10.0b and uvm-1.0p1, the compiler reports waring as follows: vlog -timescale "1ns/1ps" -mfcu -incr -suppress 2181 +acc=rmb -writetoplevels questa.tops +incdir+../../../uvm-1.0p1/src +incdir+../../src ../../../uvm-1.0p1/src/uvm.sv test.sv QuestaSim vlog 10.0b Compiler 2011.05 May 5 2011 -- Compiling package uvm_pkg -- Compiling package uvm_phase_awareness_pkg -- Compiling package blk_a_pkg ** Warning: ../../src/blk_a_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. -- Compiling package blk_b_pkg ** Warning: ../../src/blk_b_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. -- Compiling package rst_pkg -- Compiling package test_pkg -- Compiling package test_a_pkg -- Compiling package test_b_pkg -- Compiling program top Top level modules: top When I simulates it after compiling, the simulator reports errors as follow: # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test -do {do wave.do; run -all; q} -l questa.log -novopt -sv_lib ../../../uvm-1.0p1/lib/uvm_dpi top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_pkg # Loading sv_std.std # Loading work.uvm_pkg # Loading work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_pkg # Loading work.test_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_phase_awareness_pkg # Loading work.uvm_phase_awareness_pkg # Loading work.blk_b_pkg # Loading work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_a_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_a_pkg # Loading work.blk_a_pkg # Loading work.test_a_pkg # Loading work.top # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_a_pkg::backgroundN_seq # Loading .\../../../uvm-1.0p1/lib/uvm_dpi.dll # Error loading design ################################################################# When I compiles it under the QuestaSim 10.0b and uvm-1.1, the compiler reports warings as follows: vlog -timescale "1ns/1ps" -mfcu -incr -suppress 2181 +acc=rmb -writetoplevels questa.tops +incdir+../../../uvm-1.1/src +incdir+../../src ../../../uvm-1.1/src/uvm.sv test.sv QuestaSim vlog 10.0b Compiler 2011.05 May 5 2011 -- Compiling package uvm_pkg -- Compiling package uvm_phase_awareness_pkg -- Compiling package blk_a_pkg ** Warning: ../../src/blk_a_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'start_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check t he spelling of the name 'start_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'finish_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'finish_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'get_sequencer' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please chec k the spelling of the name 'get_sequencer'. -- Compiling package blk_b_pkg ** Warning: ../../src/blk_b_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'start_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check t he spelling of the name 'start_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'finish_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'finish_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'get_sequencer' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please chec k the spelling of the name 'get_sequencer'. -- Compiling package rst_pkg -- Compiling package test_pkg -- Compiling package test_a_pkg -- Compiling package test_b_pkg -- Compiling program top Top level modules: top When I simulates it after compiling, the simulator reports errors as follow: # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test -do {do wave.do; run -all; q} -l questa.log -novopt -sv_lib ../../../uvm-1.1/lib/uvm_dpi top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_pkg # Loading sv_std.std # Loading work.uvm_pkg # Loading work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_pkg # Loading work.test_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_phase_awareness_pkg # Loading work.uvm_phase_awareness_pkg # Loading work.blk_b_pkg # Loading work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_a_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_a_pkg # Loading work.blk_a_pkg # Loading work.test_a_pkg # Loading work.top # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'start_item' in $root.start_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'finish_item' in $root.finish_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'get_sequencer' in $root.get_sequencer. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'start_item' in $root.start_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'finish_item' in $root.finish_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'get_sequencer' in $root.get_sequencer. # Region: /blk_a_pkg::backgroundN_seq # Loading .\../../../uvm-1.1/lib/uvm_dpi.dll # Error loading design # by comparing the source code- uvm-1.0p1 and uvm-1.1-RC5, we find that the differents are in files -uvm_seqence_item and uvm_sequence_base related to the location of create_item, starte_item, finish_item and get_sequencer defined. Please to check it!!!! Thanks!!! please give someone reply to resolve this issue i am also facing same issue Quote Share this post Link to post Share on other sites
uwes 18 Report post Posted September 24, 2019 uvm-1.0p1 is pre-historic and uvm-1.1-rc* is just slightly younger. please run with a recent uvm version such as uvm-1.2 or uvm-ieee Quote Share this post Link to post Share on other sites
