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qinhailiang

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Everything posted by qinhailiang

  1. Hi, all When i read the uvm source code, I had a puzzle as follow: Why are the twelve runtime phases added into m_uvm_schedule phase instead of being added directly m_uvm_domain domain in file uvm_domain.svh? static function void add_uvm_phases(uvm_phase schedule); schedule.add(uvm_pre_reset_phase::get()); schedule.add(uvm_reset_phase::get()); schedule.add(uvm_post_reset_phase::get()); schedule.add(uvm_pre_configure_phase::get()); schedule.add(uvm_configure_phase::get()); schedule.add(uvm_post_configure_phase::get()); schedule.add(uvm_pre_main_phase::get()); schedule.add(uvm_main_phase::get()); schedule.add(uvm_post_main_phase::get()); schedule.add(uvm_pre_shutdown_phase::get()); schedule.add(uvm_shutdown_phase::get()); schedule.add(uvm_post_shutdown_phase::get()); endfunction static function uvm_domain get_uvm_domain(); if (m_uvm_domain == null) begin m_uvm_domain = new("uvm"); m_uvm_schedule = new("uvm_sched", UVM_PHASE_SCHEDULE); add_uvm_phases(m_uvm_schedule); m_uvm_domain.add(m_uvm_schedule); end return m_uvm_domain; endfunction Could the two functions be mergered one function as follow? static function uvm_domain get_uvm_domain(); if (m_uvm_domain == null) begin m_uvm_domain = new("uvm"); m_uvm_domain.add(uvm_pre_reset_phase::get()); m_uvm_domain.add(uvm_reset_phase::get()); m_uvm_domain.add(uvm_post_reset_phase::get()); m_uvm_domain.add(uvm_pre_configure_phase::get()); m_uvm_domain.add(uvm_configure_phase::get()); m_uvm_domain.add(uvm_post_configure_phase::get()); m_uvm_domain.add(uvm_pre_main_phase::get()); m_uvm_domain.add(uvm_main_phase::get()); m_uvm_domain.add(uvm_post_main_phase::get()); m_uvm_domain.add(uvm_pre_shutdown_phase::get()); m_uvm_domain.add(uvm_shutdown_phase::get()); m_uvm_domain.add(uvm_post_shutdown_phase::get()); end return m_uvm_domain; endfunction
  2. Hi, all Thanks for your valuable informaiton. It is very useful to understand the cast operation. Thank you again. BR QIN
  3. Hi, Alan I modified the code as you said above, it worked well. Thank you for your value information. BR QIN
  4. Hi, Zhuang Thank you for your value information. I also want to know what the assignment of P1 with P2 does? BR
  5. Hi, Zhuang I modified the source code as you said as follow: class BasePacket; int A = 1; int C = 2; function void printA; $display("BasePacket::A is %d", A); endfunction : printA virtual function void printC; $display("BasePacket::C is %d", C); endfunction : printC endclass : BasePacket class My_Packet extends BasePacket; int A = 3; int C = 4; function void printA; $display("My_Packet::A is %d", A); endfunction: printA virtual function void printC; $display("My_Packet::C is %d", C); endfunction : printC endclass : My_Packet BasePacket P1 = new; My_Packet P2; initial begin //P1 = P2; P1.printA; P1.printC; $cast(P2, P1); P2.printA; P2.printC; end The simulator also reported fatal error as follow: # BasePacket::A is 1 # BasePacket::C is 2 # ** Error: (vsim-3971) $cast to type 'class work.obc_pkg_sv_unit::My_Packet' from 'class work.obc_pkg_sv_unit::BasePacket' failed in file ../../sv/top/bip4_vtop.sv at line 77. # Time: 0 ps Iteration: 0 Instance: /bip4_vtop # ** Fatal: (SIGSEGV) Bad handle or reference. # Time: 0 ps Iteration: 0 Process: /bip4_vtop/#INITIAL#73 File: ../../sv/top/bip4_vtop.sv # Fatal error in Function obc_pkg_sv_unit/My_Packet::printA at ../../sv/top/bip4_vtop.sv line 20 Could you like to explain the reason? Thank you in advanced. BR QIN
  6. Hi, all //Case One class BasePacket; int A; endclass : BasePacket class My_Packet extends BasePacket; int C; endclass : My_Packet class BaseTest; BasePacket PB[string]; virtual function void Create_PKT(string s); PB = new(); endfunction : Create_PKT virtual function void Configure_PKT(string s); PB.A = 1; endfunction : Configure_PKT virtual function void printP(string s); $display("BaseTest::PB[%s].A is %d", s, PB.A); endfunction : printP endclass : BaseTest class My_Test extends BaseTest; virtual function void Create_PKT(string s); My_Packet MP = new(); PB = MP; endfunction : Create_PKT virtual function void Configure_PKT(string s); // My_Packet mp; super.Configure_PKT(s); My_Packet mp; $cast(mp, PB); mp.C = 2; PB = mp; endfunction : Configure_PKT virtual function void printP(string s); // My_Packet mp; super.printP(s); My_Packet mp; $cast(mp, PB); $display("My_test::PB[%s].C is %d", s, mp.C); endfunction : printP endclass : My_Test BaseTest T1 = new(); My_Test T2 = new(); initial begin T1.Create_PKT("StringBase"); T1.Configure_PKT("StringBase"); T1.printP("StringBase"); T2.Create_PKT("MY_String"); T2.Configure_PKT("MY_String"); T2.printP("MY_String"); end //Output Information (Compiler Report Error) // //near "mp": syntax error, unexpected IDENTIFIER, expecting # //Case Two class BasePacket; int A; endclass : BasePacket class My_Packet extends BasePacket; int C; endclass : My_Packet class BaseTest; BasePacket PB[string]; virtual function void Create_PKT(string s); PB = new(); endfunction : Create_PKT virtual function void Configure_PKT(string s); PB.A = 1; endfunction : Configure_PKT virtual function void printP(string s); $display("BaseTest::PB[%s].A is %d", s, PB.A); endfunction : printP endclass : BaseTest class My_Test extends BaseTest; virtual function void Create_PKT(string s); My_Packet MP = new(); PB = MP; endfunction : Create_PKT virtual function void Configure_PKT(string s); My_Packet mp; super.Configure_PKT(s); //My_Packet mp; $cast(mp, PB); mp.C = 2; PB = mp; endfunction : Configure_PKT virtual function void printP(string s); My_Packet mp; super.printP(s); //My_Packet mp; $cast(mp, PB); $display("My_test::PB[%s].C is %d", s, mp.C); endfunction : printP endclass : My_Test BaseTest T1 = new(); My_Test T2 = new(); initial begin T1.Create_PKT("StringBase"); T1.Configure_PKT("StringBase"); T1.printP("StringBase"); T2.Create_PKT("MY_String"); T2.Configure_PKT("MY_String"); T2.printP("MY_String"); end //Output Information // //# BaseTest::PB[stringBase].A is 1 //# BaseTest::PB[MY_String].A is 1 //# My_test::PB[MY_String].C is 2 I designed two cases as above, ran case one, the simulator reported error as above. Would like to tell me the different of the declaration class handle before and after the super call? Thank you in advanced. BR QIN
  7. Hi, all I has an example as follow: class BasePacket; int A = 1; int C = 2; function void printA; $display("BasePacket::A is %d", A); endfunction : printA virtual function void printC; $display("BasePacket::C is %d", C); endfunction : printC endclass : BasePacket class My_Packet extends BasePacket; int A = 3; int C = 4; function void printA; $display("My_Packet::A is %d", A); endfunction: printA virtual function void printC; $display("My_Packet::C is %d", C); endfunction : printC endclass : My_Packet BasePacket P1 = new; My_Packet P2 = new; Case one: initial begin //P1 = P2; P1.printA; P1.printC; $cast(P2, P1); P2.printA; P2.printC; end ... # BasePacket::A is 1 # BasePacket::C is 2 # ** Error: (vsim-3971) $cast to type 'class work.obc_pkg_sv_unit::My_Packet' from 'class work.obc_pkg_sv_unit::BasePacket' failed in file ../../sv/top/bip4_vtop.sv at line 80. # Time: 0 ps Iteration: 0 Instance: /bip4_vtop # My_Packet::A is 3 # My_Packet::C is 4 ... Case Two: initial begin P1 = P2; P1.printA; P1.printC; $cast(P2, P1); P2.printA; P2.printC; end ... # BasePacket::A is 1 # My_Packet::C is 4 # My_Packet::A is 3 # My_Packet::C is 4 ... Case one, I didn't assign P1 with P2, the simulator reported error information as above; the type of P1 is not a superclass of the P2 type? Case twon, I assign P1 with P2 at the begbining, the simulator reported normally as above; Why the assignment of P2 with P1 is cast-compatible after assigned P1 with P2? How to do the simulator judge the cast-compatible? So I want to know what the assignment of P1 with P2 does? Thank you in advanced. BR QIN
  8. when the m_pool.add(obj, q) is called by the function add(T obj, uvm_callback cb, uvm_apprepend ordering=UVM_APPEND) in the class uvm_callbacks #(type T=uvm_object, type CB=uvm_callback), if q (i.e the entry you said) is null, the q will be newed, i.e the q (the entry) is not null.
  9. Hi, all There is a piece of code in the function m_add_tw_cbs of the uvm_typed_callbacks#(type T=uvm_object) of the file uvm_callback.sv as follow: if(m_t_inst.m_pool.first(obj)) begin do begin if($cast(me,obj)) begin q = m_t_inst.m_pool.get(obj); if(q==null) begin q=new; m_t_inst.m_pool.add(obj,q); end if(m_cb_find(q,cb) == -1) begin if(ordering == UVM_APPEND) q.push_back(cb); else q.push_front(cb); end end end while(m_t_inst.m_pool.next(obj)); end I want to know whether the red piece is worthless ? Thank you in advanced! BR QIN
  10. Hi, all We have one monitor and one driver as follow: class monitor extends uvm_monitor; `uvm_component_utils(monitor) function new(string name, uvm_component parent); super.new(name, parent); endfunction virtual task post_shutdown_phase(uvm_phase phase); #50ns; `uvm_info(get_type_name(), "Monitor is printing at post_shutdown_phase executing...", UVM_LOW ) endtask: post_shutdown_phase virtual function void phase_ready_to_end(uvm_phase phase); if(phase.get_name == "post_shutdown") `uvm_info(get_type_name(), "Monitor is printing at phase_ready_to_end...", UVM_LOW ) endfunction: phase_ready_to_end virtual function void phase_ended(uvm_phase phase); if(phase.get_name == "post_shutdown") `uvm_info(get_type_name(), "Monitor is printing at phase_ended...", UVM_LOW ) endfunction: phase_ended endclass : monitor class driver extends uvm_driver; `uvm_component_utils(driver) function new(string name, uvm_component parent); super.new(name); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this, "Starting test"); #100ns; `uvm_info(get_type_name(), "Driver is printing at run_phase executing...", UVM_LOW ) phase.drop_objection(this, "Finishing test"); endtask: run_phase virtual function void phase_ready_to_end(uvm_phase phase); if(phase.get_name == "run") `uvm_info(get_type_name(), "Driver is printing at phase_ready_to_end...", UVM_LOW ) endfunction: phase_ready_to_end virtual function void phase_ended(uvm_phase phase); if(phase.get_name == "run") `uvm_info(get_type_name(), "Driver is printing at phase_ended...", UVM_LOW ) endfunction: phase_ended endclass: driver when it run one of cases, it printed the information as follow: # UVM_INFO @ 0: reporter [RNTST] Running test tc_read_ver_reg... # UVM_INFO ../../monitor.sv(41) @ 0: uvm_test_top.tb.agent.monitor [monitor] Monitor is printing at phase_ready_to_end... # UVM_INFO ../../monitor.sv(35) @ 50000: uvm_test_top.tb.agent.monitor [monitor] Monitor is printing at post_shutdown_phase executing... # UVM_INFO ../../driver.sv(22) @ 100000: uvm_test_top.tb.agent.driver [driver] Driver is printing at run_phase executing... # UVM_INFO ../../driver.sv(28) @ 100000: uvm_test_top.tb.agent.driver [driver] Driver is printing at phase_ready_to_end... # UVM_INFO ../../monitor.sv(48) @ 100000: uvm_test_top.tb.agent.monitor [monitor] Monitor is printing at phase_ended... # UVM_INFO ../../driver.sv(34) @ 100000: uvm_test_top.tb.agent.driver [driver] Driver is printing at phase_ended... # The post_shutdown_phase of the monitor reached to phase_ready_to_end at 0, but it's task post_shutdown_phase did not finish until @ 50000. What is wrong with it? Thank you in advanced! BR QIN
  11. Hi, all Why is not the 12 realtime phases directly wrapped by m_uvm_domain but also the m_uvm_schedule is inserted between m_uvm_domain and the 12 realtime phases? Thank you in advanced! BR QIN
  12. Hi, all I fond the function uvm_report_error is called in uvm_object.svh when I read the UVM-1.1d source code, but the file uvm_object.svh is compiled before the file uvm_globals.svh in the file base.svh. Would you please tell me what is wrong with it? Thanks a lot in advanced! Best Regards QIN
  13. Hi, all when is the size of the queue lock_list greater than one in uvm_sequencer_base.sv file? Could you like to give us some examples? Thanks in advanced! BR QIN
  14. Hi, All there is a task as follow in uvm_globals.sv file. //---------------------------------------------------------------------------- // // Task: uvm_wait_for_nba_region // // Callers of this task will not return until the NBA region, thus allowing // other processes any number of delta cycles (#0) to settle out before // continuing. See <uvm_sequencer_base::wait_for_sequences> for example usage. // //---------------------------------------------------------------------------- task uvm_wait_for_nba_region; string s; int nba; int next_nba; //If `included directly in a program block, can't use a non-blocking assign, //but it isn't needed since program blocks are in a seperate region. `ifndef UVM_NO_WAIT_FOR_NBA next_nba++; nba <= next_nba; @(nba); `else repeat(`UVM_POUND_ZERO_COUNT) #0; `endif endtask For example, it is used in the task wait_for_sequences in uvm_sequencer_base.sv file Who would like to explain the function of the uvm_wait_for_nba_region in details? Best Regards QIN
  15. Hi, UWE Thanks for your reply. I understand your explanation! thanks again. Best Regards QIN
  16. Hi, all i confused about the different between run_phase and other 12 runtime phase at bellow two case: First Case: task monitor::run_phase(uvm_phase pahse); super.run_phase(phase); #50; `uvm_info("RUN_PHASE", "Monitor Run_phase Starting", UVM_NONE) endtask task driver::main_phase(uvm_phase pahse); super.main_phase(phase); phase.raise_objection(this); #100; `uvm_info("MAIN_PHASE", "Driver Main_phase Starting", UVM_NONE) phase.drop_objection(this); endtask In the case, raise objection in driver‘s main_phase task, does not raise objection in the monitor's run_phase task the run_phase and main_phase work as expected! Second Case: task monitor::run_phase(uvm_phase pahse); super.run_phase(phase); phase.raise_objection(this); #100; `uvm_info("RUN_PHASE", "Monitor Run_phase Starting", UVM_NONE) phase.drop_objection(this); endtask task driver::main_phase(uvm_phase pahse); super.main_phase(phase); #50; `uvm_info("MAIN_PHASE", "Driver Main_phase Starting", UVM_NONE) endtask In the case, raise objection in the monitor's run_phase task, does not raise objection in the driver’s main_phase task The run_phase work expected, but the main_phase task in driver does not output any information, in other words, it seems like the main_phase task is not scheduled! Who know the reason? BR QIN
  17. Hi, Jadec Thanks for your reply I want to put all of elements of an whole array into an queue every time, can define as above? and can do as follow? queue.push_back(valid_data); if no, could you please to tell me other methods? Thanks in advance BR
  18. Now, I has defined an array as follow: bit [7:0] valid_data[8064]; How to define an queue and make the array cached into it? Thanks in advance. BR
  19. I downloaded the UVM Run-Time Phases Primer (v0.5.1) from the UVM World Contributions column. ############################################################### When I compiles it under the QuestaSim 10.0b and uvm-1.0p1, the compiler reports waring as follows: vlog -timescale "1ns/1ps" -mfcu -incr -suppress 2181 +acc=rmb -writetoplevels questa.tops +incdir+../../../uvm-1.0p1/src +incdir+../../src ../../../uvm-1.0p1/src/uvm.sv test.sv QuestaSim vlog 10.0b Compiler 2011.05 May 5 2011 -- Compiling package uvm_pkg -- Compiling package uvm_phase_awareness_pkg -- Compiling package blk_a_pkg ** Warning: ../../src/blk_a_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. -- Compiling package blk_b_pkg ** Warning: ../../src/blk_b_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. -- Compiling package rst_pkg -- Compiling package test_pkg -- Compiling package test_a_pkg -- Compiling package test_b_pkg -- Compiling program top Top level modules: top When I simulates it after compiling, the simulator reports errors as follow: # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test -do {do wave.do; run -all; q} -l questa.log -novopt -sv_lib ../../../uvm-1.0p1/lib/uvm_dpi top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_pkg # Loading sv_std.std # Loading work.uvm_pkg # Loading work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_pkg # Loading work.test_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_phase_awareness_pkg # Loading work.uvm_phase_awareness_pkg # Loading work.blk_b_pkg # Loading work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_a_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_a_pkg # Loading work.blk_a_pkg # Loading work.test_a_pkg # Loading work.top # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_a_pkg::backgroundN_seq # Loading .\../../../uvm-1.0p1/lib/uvm_dpi.dll # Error loading design ################################################################# When I compiles it under the QuestaSim 10.0b and uvm-1.1, the compiler reports warings as follows: vlog -timescale "1ns/1ps" -mfcu -incr -suppress 2181 +acc=rmb -writetoplevels questa.tops +incdir+../../../uvm-1.1/src +incdir+../../src ../../../uvm-1.1/src/uvm.sv test.sv QuestaSim vlog 10.0b Compiler 2011.05 May 5 2011 -- Compiling package uvm_pkg -- Compiling package uvm_phase_awareness_pkg -- Compiling package blk_a_pkg ** Warning: ../../src/blk_a_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'start_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check t he spelling of the name 'start_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'finish_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'finish_item'. ** Warning: ../../src/blk_a_seq_lib.svh(163): (vlog-7046) The name 'get_sequencer' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please chec k the spelling of the name 'get_sequencer'. -- Compiling package blk_b_pkg ** Warning: ../../src/blk_b_seq_lib.svh(159): (vlog-7046) The name 'create_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'create_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'start_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check t he spelling of the name 'start_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'finish_item' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please check the spelling of the name 'finish_item'. ** Warning: ../../src/blk_b_seq_lib.svh(163): (vlog-7046) The name 'get_sequencer' is not found. The tool will treat the name as a reference starting at $root. If this is unexpected please chec k the spelling of the name 'get_sequencer'. -- Compiling package rst_pkg -- Compiling package test_pkg -- Compiling package test_a_pkg -- Compiling package test_b_pkg -- Compiling program top Top level modules: top When I simulates it after compiling, the simulator reports errors as follow: # vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test -do {do wave.do; run -all; q} -l questa.log -novopt -sv_lib ../../../uvm-1.1/lib/uvm_dpi top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.top # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_pkg # Loading sv_std.std # Loading work.uvm_pkg # Loading work.rst_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_pkg # Loading work.test_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.uvm_phase_awareness_pkg # Loading work.uvm_phase_awareness_pkg # Loading work.blk_b_pkg # Loading work.test_b_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.test_a_pkg # Refreshing E:\i-TDM\eCodes\sim\phasing_primer_v5.1\tests\03test_ab_reset\work.blk_a_pkg # Loading work.blk_a_pkg # Loading work.test_a_pkg # Loading work.top # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'start_item' in $root.start_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'finish_item' in $root.finish_item. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_b_seq_lib.svh(163): Unresolved reference to 'get_sequencer' in $root.get_sequencer. # Region: /blk_b_pkg::backgroundM_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(159): Unresolved reference to 'create_item' in $root.create_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'start_item' in $root.start_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'finish_item' in $root.finish_item. # Region: /blk_a_pkg::backgroundN_seq # ** Error: (vsim-3043) ../../src/blk_a_seq_lib.svh(163): Unresolved reference to 'get_sequencer' in $root.get_sequencer. # Region: /blk_a_pkg::backgroundN_seq # Loading .\../../../uvm-1.1/lib/uvm_dpi.dll # Error loading design # by comparing the source code- uvm-1.0p1 and uvm-1.1-RC5, we find that the differents are in files -uvm_seqence_item and uvm_sequence_base related to the location of create_item, starte_item, finish_item and get_sequencer defined. Please to check it!!!! Thanks!!!
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