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Compilation error regarding illegal class assignment


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Hey!

I've got a compilation error in QuestaSim bugging me for days now.

That's the error:

Error: (vsim-3978) ../src/reg_sequence.sv(27): Illegal assignment to class type uvm_component [in mtiUvm/uvm_pkg::uvm_component] from class type reg_sequence [in work/top_sv_unit::reg_sequence]

There is a register model which I'm trying to pass to a sequence by using the uvm_config_db. The register model is derived from uvm_reg_block and uses the uvm_object_utils macro.

In my environment I create an instance of the register model and pass the handle to the uvm_config_db.

reg_model rm;
...
// create reg_model
...
uvm_config_db#(reg_model)::set(this, "*.*reg_sequence*", "register_model", rm);

In the sequence I've got a variable of type reg_model and I would like to use the handle from the uvm_config_db for this variable.

reg_model model;
...
uvm_config_db#(reg_model)::get(this, "", "register_model", model);

Can anyone tell me why this is not working and the error occurs?

Thanks in advance!

Regards,

Johannes

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