SeanChou Posted April 6, 2011 Report Share Posted April 6, 2011 Hi Cadence Gentlemen, Thanks for your answers in advanced. 1. To maintain corresponding data structure (packet.h, packet.sv) in 2 languages manually is easily to introduce error. especially pack/unpack orders. does cadence plan to provide user some translation script that could generate another implementation? 2. How the synchronization is handled between both languages? are they always sync together or is it possible to let SC temporal decoupling from SV, (for example to speed up the OS booting time in SC without interrupt from idle DUT.) 3. I heard there would be a new standard for sc-sv interoperability last time (URL below), just curious if there is any progress revealed? http://www.uvmworld.org/forums/showthread.php?118-Would-UVM1.0-standardize-SV-SC-TLM-Interface-%28as-mentioned-in-UVM1.0-Raodmap%29 Quote Link to comment Share on other sites More sharing options...
zeevk Posted April 6, 2011 Report Share Posted April 6, 2011 Hi SeanChou, I'll take a stab at the first two items in your list. #1 - yes, Cadence provides a tool that automates that exact part - mapping class declarations in one language to another, so that they can be used for multi-language communication (e.g. via TLM ports). The utility is called 'mltypemap' and it's documented in the Incisive docs. Please look it up for it for all the details. #2 - the question seems to stem from a HW/SW verification effort. We have quite a bit in that domain, so I'd recommend you look up things like ISX. Zeev. Quote Link to comment Share on other sites More sharing options...
SeanChou Posted April 7, 2011 Author Report Share Posted April 7, 2011 Thanks for Zeevk's response. 1. I still need some hint for the usage of mltypemap after referring to the UVM-ML reference and "mltypemap -help". 1.1 reference says it could map sv to e, could it to sc also? 1.2 is there also an example that I could refer to? 2. After taking a glance at ISX data sheet, it provides more function than expected and complex. The purpose is to leverage some existed UVM scenario to verify not only the h/w but a system. which could be compiled with OSCI libraries with g++. should I need ISX solution to realize temporal decoupling? Quote Link to comment Share on other sites More sharing options...
zeevk Posted April 7, 2011 Report Share Posted April 7, 2011 Hi SeanChou, Regarding #1 - yes, mltypemap can map SV classes to SystemC. There is an example in the documentation - bring up cdnshelp in the Incisive 10.2 release, and search for mltypemap. The examples section includes a SV -> SystemC example (section 5.1.2). I'll ask someone else to follow up on your #2 question. Zeev. Quote Link to comment Share on other sites More sharing options...
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