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Compiling UV

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I bought a couple of books on UVM and am intrigued by it.  After reading through the first book, I wanted to give things a try.  We do not have any SystemVerilog licenses here at work, so I decided to try to compile the UVM using Vivado's included simulator.  I know that Xilinx hasn't announced official support for the UVM, but Vivado does support SystemVerilog, though it appears to be limited to design constructs.  Regardless, I decided to proceed.


When compiling I get several errors.  I know that some are likely limitations on the Xilinx simulator.  But some appear to be more generic in nature and I'm not sure if it is a Xilinx issue.  I downloaded the UVM 1.2 release and tried to compile using Xilinx's 'xvlog' command with:


xvlog --sv --include uvm-1.2/src uvm-1.2/src/uvm.sv


And the first few errors:


ERROR: [VRFC 10-91] process is not declared [uvm-1.2/src/base/uvm_coreservice.svh:155]
ERROR: [VRFC 10-1432] task or function check with ref arguments must be automatic [uvm-1.2/src/base/uvm_spell_chkr.svh:70]
ERROR: [VRFC 10-91] process is not declared [uvm-1.2/src/base/uvm_resource.svh:879]
ERROR: [VRFC 10-1432] task or function sort_by_precedence with ref arguments must be automatic [uvm-1.2/src/base/uvm_resource.svh:954]
ERROR: [VRFC 10-1432] task or function get_highest_precedence with ref arguments must be automatic [uvm-1.2/src/base/uvm_resource.svh:1650]
The first error appears to be due to Xilinx not supporting the building 'process' class.  I get this one.
But the next one seems strange to me.  From uvm_spell_chkr.svh, line 70:
static function bit check ( /* const */ ref tab_t strtab, input string s);
The error text implies this is a language requirement.  That is, because 'check' is a static function, the ref argument must be automatic.  From a post I found at Verification Academy (see https://verificationacademy.com/forums/systemverilog/what-meant-reference-argument-must-be-automatic), the LRM says in 13.5.2:
It shall be illegal to use argument passing by reference for subroutines with a lifetime of static.


So it seems that this line violates the LRM.  Yet clearly the UVM 1.2 release works with numerous other simulators which are implemented from the same LRM.


Is this issue Xilinx specific?  Or are there changes to the UVM for these types of errors?

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There's a difference between static function and function static. The rule in 13.5.2 refers to subprograms declared with a lifetime of static, e.g.


function static ...

task static ...


In the UVM code, the declaration is


static function


which is a static method of a class - section 8.10 in the LRM.





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