I bought a couple of books on UVM and am intrigued by it. After reading through the first book, I wanted to give things a try. We do not have any SystemVerilog licenses here at work, so I decided to try to compile the UVM using Vivado's included simulator. I know that Xilinx hasn't announced official support for the UVM, but Vivado does support SystemVerilog, though it appears to be limited to design constructs. Regardless, I decided to proceed.
When compiling I get several errors. I know that some are likely limitations on the Xilinx simulator. But some appear to be more generic in