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  1. I bought a couple of books on UVM and am intrigued by it. After reading through the first book, I wanted to give things a try. We do not have any SystemVerilog licenses here at work, so I decided to try to compile the UVM using Vivado's included simulator. I know that Xilinx hasn't announced official support for the UVM, but Vivado does support SystemVerilog, though it appears to be limited to design constructs. Regardless, I decided to proceed. When compiling I get several errors. I know that some are likely limitations on the Xilinx simulator. But some appear to be more generic in
  2. First off, thank you for your responses! You have been very helpful. I'm a bit confused here. Say I had the following class definitions: class base { public: virtual void write(int) = 0; virtual int read() = 0; }; I can define a template class like this: template<typename T> class derived : public base { public: virtual void write(int) { // Do whatever is specific to convert int to T } // Override specific to T virtual void write(T) { } virtual int read() { // Do whatever is specific to convert T to int } /
  3. Sure. It appears that the design decision when implementing SystemC (or perhaps even part of the standard) was the use of templates. Or at least, templates deep enough into the class hierarchy to preclude the use of polymorphism to pass around base pointers with relevant methods (though Phillip does point out sc_port_base below, but more on this point in a bit). I get the need for a factory. That isn't the issue. Rather, it was how to read/write a port from a base class, when I don't see a base class that will let me do that. I misread the hierarchy. I followed the template paramet
  4. I'm working on a small simulation library based on SystemC for a research project. What I'd like to do is have the I/O from a testbench module be dynamically determined at runtime (perhaps through some sort of configuration file). The point is to avoid recompilation and have the testbench dynamically configure itself to accommodate the UUT. The problem is not that I cannot traverse the hierarchy (I've figured that out) and get the ports. The problem is that I cannot seem to dynamically generate a "database". Since all the ports are templated, I can't generate a generic data structur
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