karandeep963 Posted December 1, 2014 Report Share Posted December 1, 2014 Hello All, module top; initial begin bit data_source []; byte unsigned pack_data[]; data_source = new[3]; pack_data = new[2]; for(int i = 0 ; i < (data_source.size()) ; i++)begin if ((i %2) == 0)data_source[i] = 1'b1; $display("INITIALIZED VALUE OF DATA SOURCE [%d] = 0x%x",i,data_source[i]); end foreach(pack_data[i])$display("\nUNINITIALIZED VALUE OF PACKED ARRAY[%d] = 0x%x",i,pack_data[i]); // Casting Little endianess pack_data = {<<{data_source}}; foreach(pack_data[i])$display("\nVALUE OF {LITTLE ENDIAN} PACKED ARRAY[%d] = 0x%x",i,pack_data[i]); // Casting BIG endianess pack_data = {>>{data_source}}; foreach(pack_data[i])$display("\nVALUE OF {BIG ENDIAN} PACKED ARRAY[%d] = 0x%x",i,pack_data[i]); end endmodule:top generates the following results: Both the little endian and big endian results same ??? INITIALIZED VALUE OF DATA SOURCE [ 0] = 0x1 INITIALIZED VALUE OF DATA SOURCE [ 1] = 0x0 INITIALIZED VALUE OF DATA SOURCE [ 2] = 0x1 UNINITIALIZED VALUE OF PACKED ARRAY[ 0] = 0x00 UNINITIALIZED VALUE OF PACKED ARRAY[ 1] = 0x00 VALUE OF {LITTLE ENDIAN} PACKED ARRAY[ 0] = 0xa0 VALUE OF {BIG ENDIAN} PACKED ARRAY[ 0] = 0xa0 but if keeping data_source = new[any even number]; // lets say keeping it 4 the following results looks fine VALUE OF {LITTLE ENDIAN} PACKED ARRAY[ 0] = 0x50 VALUE OF {BIG ENDIAN} PACKED ARRAY[ 0] = 0xa0 Can anybody help me with this ?? Thanks , KS Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted December 1, 2014 Report Share Posted December 1, 2014 A suggestion for this type of questions: use StackOverflow. There is already a category for SystemVerilog and the you're more likely to get a quick answer. karandeep963 1 Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted December 1, 2014 Report Share Posted December 1, 2014 Also, I remember reading some blog posts on the topic: http://bryan-murdock.blogspot.de/2014/10/systemverilog-streaming-operator.html http://bryan-murdock.blogspot.de/2014/10/more-systemverilog-streaming-examples.html Have a look at these and see if you can figure out what's happening. karandeep963 1 Quote Link to comment Share on other sites More sharing options...
apfitch Posted December 2, 2014 Report Share Posted December 2, 2014 I think the key sentence is "If the target represents a dynamically sized variable, such as aqueue or dynamic array, the variable is resized to accommodate the entire stream. If, after resizing, thevariable is larger than the stream, the stream is left-aligned and zero-filled on the right." So in your first case, the resulting stream is 101 (length 3) whether you stream it >> or <<. You then assign it to a dynamic array of byte. You therefore end up with 10100000 in a dynamic array is size 1. In the case of data source 4, you start with the pattern data_source [0] = 1, data_source[1] = 0, data_source[2] = 1, data_source [3] = 0 When you stream that with << or >> you get two four bit values, either 0101 or 1010 When you assign these to the dynamic array you get either 01010000 10100000 Q.E.D regards Alan karandeep963 1 Quote Link to comment Share on other sites More sharing options...
karandeep963 Posted December 2, 2014 Author Report Share Posted December 2, 2014 Many Thanks TUDOR and ALAN, That helps a lot. Thanks to Bryan's Posts as well. Indeed the tricks needed to use it !! Quote Link to comment Share on other sites More sharing options...
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