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problem on set_config_int


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Hi,

I defined variant in my scoreboard as this:

int unsigned initial_id;

...

`uvm_component_utils_begin(...);

...

`uvm_field_int(initial_id,UVM_DEFAULT)

`uvm_components_utils_end

And then I hope to assign values to initial_id from my test environment as this:

class dut_test extends uvm_test;

...

function void build();

...

set_config_int("scoreboard","initial_id",20'hffff0);

endfunction

endclass

I checked topolopy and see this results:

...

scoreboard

...

initial_id integral 32 'h0

To my surprise, I can see initial_id from the tree, but I can't change the value of initial_id, I got the warning:

UVM_WARNING: .... uvm_test_top [CFGNTS] No get_config_int() call ever matched the following set_config_int() call from component uvm_test_top(dut_test): Integral: component=scoreboard, field=initial_id, value= ...

can any expert help me? thanks

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In fact, I can use set_config_* in other module successfully, such as in driver and monitor, but I failed in scoreboard. Quite strange...

hi,

just guessing that the set_config*(logical_path,field,value) does not apply to the logical path of your scoreboard. you somehow also indicate that because you say that the set_config works on driver+monitor.

try one of following:

- set_config_int("*","initial_id",20'hffff0)

- set_config_int(<path.to.scoreboard>.get_full_name(),"initial_id",20'hffff0)

- set_config_int("*.scoreboard","initial_id",20'hffff0)

regards

/uwe

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well,

if the first variant doesnt work (the most generic kind) the issue might be somewhere else.

- logical name different than "scoreboard", (or the fieldname)

- set-config after component has been built

- not using the automation (not using super.* in the appropriate hooks)

- maybe other issues

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Hi uwes,

I checked the code:

- logical name different than "scoreboard", (or the fieldname)

Ans: I believe name is right.

- set-config after component has been built

Ans: this give me some tips.

now in my code I did it like this:

class dut_test_simple extends uvm_test;

`uvm_component_utils(dut_test_simple)

dut_env env;

dut_scoreboard scoreboard;

...

function build();

super.build();

...

env = dut_env::type_id::create("env",this);

scoreboard = dut_scoreboard::type_id::create("scoreboard",this);

endfunction : build

...

endclass:dut_test_simple

class dut_test_extreme_case1 extends dut_test_simple;

`uvm_component_utils(dut_test_extreme_case1)

...

function build();

super.build();

set_config_int("scoreboard", "initial_id",20'hffff0);

...

endfunction : build

endclass : dut_test_extreme_case1

Is there anything wrong to this set_config_int? I tried to put it before super.build(), but this arise a run-time error.

regards

CY

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Hi,

in fact I tried to put set_config before super.build() in function build, but this arise run-time error. I put the set_config after super.build and this time set_config doesn't work for scoreboard, but it work for driver/monitor!

In order to find the reason, I declare the debug scoreboard to see if this is the case.

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Name Type Size Value

----------------------------------------------------------------------

uvm_test_top dut_test_extreme_c+ - @787

db_scoreboard dut_scoreboard - @983

item_vld0_export uvm_analysis_imp_v+ - @1131

item_vld1_export uvm_analysis_imp_v+ - @1197

item_vld2_export uvm_analysis_imp_v+ - @1262

item_vld3_export uvm_analysis_imp_v+ - @1327

disable_scoreboard integral 1 'h0

initial_id integral 32 'h0

env dut_env - @924

adc_agent dut_adc_agent - @1063

adc_driver dut_adc_driver - @1876

rsp_port uvm_analysis_port - @2988

sqr_pull_port uvm_seq_item_pull_+ - @2923

adc_monitor dut_adc_monitor - @1677

seq_out_imp uvm_analysis_imp - @1803

adc_sequencer dut_adc_sequencer - @1738

rsp_export uvm_analysis_export - @1950

seq_item_export uvm_seq_item_pull_+ - @2717

seq_out_port uvm_analysis_port - @2801

default_sequence string 11 dut_adc_seq

count integral 32 -1

max_random_count integral 32 'd10

sequences array 4 -

[0] string 19 uvm_random_sequence

[1] string 23 uvm_exhaustive_sequ+

[2] string 19 uvm_simple_sequence

[3] string 11 dut_adc_seq

max_random_depth integral 32 'd4

num_last_reqs integral 32 'd1

num_last_rsps integral 32 'd1

is_active uvm_active_passive+ 1 UVM_ACTIVE

ctrl_agent0 dut_ctrl_agent0 - @1392

ctrl_driver0 dut_ctrl_driver0 - @3198

rsp_port uvm_analysis_port - @4249

sqr_pull_port uvm_seq_item_pull_+ - @4184

ctrl_monitor0 dut_ctrl_monitor0 - @2859

ctrl_dvld0 uvm_analysis_port - @3139

ctrl_sequencer dut_ctrl_sequencer - @3072

rsp_export uvm_analysis_export - @3279

seq_item_export uvm_seq_item_pull_+ - @4047

default_sequence string 12 dut_ctrl_seq

count integral 32 -1

max_random_count integral 32 'd10

sequences array 4 -

[0] string 19 uvm_random_sequence

[1] string 23 uvm_exhaustive_sequ+

[2] string 19 uvm_simple_sequence

[3] string 12 dut_ctrl_seq

max_random_depth integral 32 'd4

num_last_reqs integral 32 'd1

num_last_rsps integral 32 'd1

is_active uvm_active_passive+ 1 UVM_ACTIVE

ctrl_agent1 dut_ctrl_agent1 - @1449

ctrl_driver1 dut_ctrl_driver1 - @4457

rsp_port uvm_analysis_port - @5508

sqr_pull_port uvm_seq_item_pull_+ - @5443

ctrl_monitor dut_ctrl_monitor1 - @4120

ctrl_dvld1 uvm_analysis_port - @4398

ctrl_sequencer dut_ctrl_sequencer - @4331

rsp_export uvm_analysis_export - @4538

seq_item_export uvm_seq_item_pull_+ - @5306

default_sequence string 12 dut_ctrl_seq

count integral 32 -1

max_random_count integral 32 'd10

sequences array 4 -

[0] string 19 uvm_random_sequence

[1] string 23 uvm_exhaustive_sequ+

[2] string 19 uvm_simple_sequence

[3] string 12 dut_ctrl_seq

max_random_depth integral 32 'd4

num_last_reqs integral 32 'd1

num_last_rsps integral 32 'd1

is_active uvm_active_passive+ 1 UVM_ACTIVE

ctrl_agent2 dut_ctrl_agent2 - @1506

ctrl_driver2 dut_ctrl_driver2 - @5708

rsp_port uvm_analysis_port - @6759

sqr_pull_port uvm_seq_item_pull_+ - @6694

ctrl_monitor dut_ctrl_monitor2 - @5379

ctrl_dvld2 uvm_analysis_port - @5649

ctrl_sequencer dut_ctrl_sequencer - @5583

rsp_export uvm_analysis_export - @5789

seq_item_export uvm_seq_item_pull_+ - @6557

default_sequence string 12 dut_ctrl_seq

count integral 32 -1

max_random_count integral 32 'd10

sequences array 4 -

[0] string 19 uvm_random_sequence

[1] string 23 uvm_exhaustive_sequ+

[2] string 19 uvm_simple_sequence

[3] string 12 dut_ctrl_seq

max_random_depth integral 32 'd4

num_last_reqs integral 32 'd1

num_last_rsps integral 32 'd1

is_active uvm_active_passive+ 1 UVM_ACTIVE

ctrl_agent3 dut_ctrl_agent3 - @1563

ctrl_driver3 dut_ctrl_driver3 - @6959

rsp_port uvm_analysis_port - @8010

sqr_pull_port uvm_seq_item_pull_+ - @7945

ctrl_monitor3 dut_ctrl_monitor3 - @6630

ctrl_dvld3 uvm_analysis_port - @6900

ctrl_sequencer dut_ctrl_sequencer - @6834

rsp_export uvm_analysis_export - @7040

seq_item_export uvm_seq_item_pull_+ - @7808

default_sequence string 12 dut_ctrl_seq

count integral 32 -1

max_random_count integral 32 'd10

sequences array 4 -

[0] string 19 uvm_random_sequence

[1] string 23 uvm_exhaustive_sequ+

[2] string 19 uvm_simple_sequence

[3] string 12 dut_ctrl_seq

max_random_depth integral 32 'd4

num_last_reqs integral 32 'd1

num_last_rsps integral 32 'd1

is_active uvm_active_passive+ 1 UVM_ACTIVE

id_gen_agent dut_id_gen_agent - @1620

id_gen_driver dut_id_gen_driver - @8143

rsp_port uvm_analysis_port - @9179

sqr_pull_port uvm_seq_item_pull_+ - @9115

initial_id integral 32 'hffff3

id_gen_monitor dut_id_gen_monitor - @7881

id_gen_sequencer dut_id_gen_sequenc+ - @8085

rsp_export uvm_analysis_export - @8223

seq_item_export uvm_seq_item_pull_+ - @8991

num_last_reqs integral 32 'd1

num_last_rsps integral 32 'd1

is_active uvm_active_passive+ 1 UVM_ACTIVE

scoreboard dut_scoreboard - @923

item_vld0_export uvm_analysis_imp_v+ - @9269

item_vld1_export uvm_analysis_imp_v+ - @9335

item_vld2_export uvm_analysis_imp_v+ - @9400

item_vld3_export uvm_analysis_imp_v+ - @9465

disable_scoreboard integral 1 'h0

initial_id integral 32 'h0

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above is the topology, sorry the "reply" changed its format.

and here is my source code:

class dut_test_simple extends uvm_test;

`uvm_component_utils(dut_test_simple)

dut_env env;

dut_scoreboard scoreboard;

function new(string name = "dut_test_simple", uvm_component parent = null);

super.new(name, parent);

endfunction : new

function void build();

super.build();

set_config_int("env.id_gen_agent.id_gen_driver","initial_id",20'h0);

set_config_string("env.adc_agent.adc_sequencer","default_sequence","dut_adc_seq");

set_config_string("env.ctrl_agent0.ctrl_sequencer","default_sequence","dut_ctrl_seq");

set_config_string("env.ctrl_agent1.ctrl_sequencer","default_sequence","dut_ctrl_seq");

set_config_string("env.ctrl_agent2.ctrl_sequencer","default_sequence","dut_ctrl_seq");

set_config_string("env.ctrl_agent3.ctrl_sequencer","default_sequence","dut_ctrl_seq");

// set_report_verbosity_level_hier(UVM_DEBUG);

env = dut_env::type_id::create("env",this);

scoreboard = dut_scoreboard::type_id::create("scoreboard",this);

endfunction : build

function void connect();

env.assign_vi(tb_uvm_top.u_dut_if);

env.ctrl_agent0.ctrl_monitor0.ctrl_dvld0.connect(scoreboard.item_vld0_export);

env.ctrl_agent1.ctrl_monitor1.ctrl_dvld1.connect(scoreboard.item_vld1_export);

env.ctrl_agent2.ctrl_monitor2.ctrl_dvld2.connect(scoreboard.item_vld2_export);

env.ctrl_agent3.ctrl_monitor3.ctrl_dvld3.connect(scoreboard.item_vld3_export);

endfunction : connect

task run();

uvm_top.print_topology();

#2000000000;

// #1000;

global_stop_request();

endtask : run

endclass : dut_test_simple

// -------------------------------------------------------

// dut_test_extreme_case1 is used to test extreme case1,

// in this case, baokuan period is set to high = 512 + 8/16/32 clock

// and low is around 512 + 8*i (i inside 1..10) clock

class dut_test_extreme_case1 extends dut_test_simple;

`uvm_component_utils(dut_test_extreme_case1)

dut_scoreboard db_scoreboard;

function new(string name = "dut_test_extreme_case1", uvm_component parent = null);

super.new(name, parent);

endfunction : new

function void build();

super.build();

set_type_override_by_type(dut_ctrl_packet::get_type(),dut_ctrl_extreme_packet::get_type());

// set_config_int("env.id_gen_agent.id_gen_driver","initial_id",20'h0);

set_config_int("env.id_gen_agent.id_gen_driver","initial_id",20'hffff3);

set_config_int("db_scoreboard","initial_id",20'hffff3);

// set_config_int("*.scoreboard","initial_id",20'hffff3);

// set_config_int("scoreboard","rec_index",20'hffff3);

db_scoreboard = dut_scoreboard::type_id::create("db_scoreboard",this);

endfunction : build

function void connect();

super.connect();

endfunction : connect

task run();

uvm_top.print_topology();

// #2000000000;

#10000;

global_stop_request();

endtask : run

endclass : dut_test_extreme_case1

did you find anything wrong in my code? thanks.

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It looks you are creating scoreboard in your test which is not recommended way as per me. you can print the topology and try to find the name of scoreboard and then using that for set_config_*.

Hi Akshay,

thanks for your reply. As I have mentioned above, I have tried to used name printed by topology and it doesn't work. Could you please tell me what is the recommend way to create scoreboard as you did? could you please provide an example? thanks.

regards

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  • 1 month later...
If you want to automatically load fields from set_config_*, you'll need to call "apply_config_settings()" function in your build() method of the recv'ing component.

Otherwise, you'll need to explicitly call get_config_* in that component.

uvm_component::build() takes care of that, so given your super.build() ends up calling the uvm_components build everything should be fine.

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