Hi Tudor, the same problem i am also facing. i just want to check if status is UVM_NOT OK, then RAL model is updating or not. then i hardcoded the status in bus2reg wantedly and i used explicit predictor method (FRONT DOOR), when i read status register from DUT then in seq, i am getting read data as 0. but at the same time when i did "get" for the status register in RAL, then my value is already updated. how to control ral updation when status is UVM_NOT_OK. ?