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UVM Register Field Coverage

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 I'm playing with a UVM Register example that initially just had register level coverage.

 My register block code (auto-generated by a tool) has a covergroup wrapped in a class and this class contains a sample method.

 The register block itself also has as sample method that calls the covergroup::sample method.


 I have this working when I use either auto-predicition or an explicit predictor.

With an explicit predicitor, I can see when I perform a write to one of my registers that my monitor sends out a transaction to the analysis port and this triggers uvm_reg_predictor::write which in turn calls uvm_reg_block::XsampleX which finally calls my reg_block::sample.

So al lthe hooks are taken care of and the coverage collection just works.


Then I added the option to collect field coverage in my register definitions.

I can see that each register definition is extended from uvm_reg, contains it own covergroup and a method called sample_values.


When I run my simulations, I see that the register covergroups are all being created but the bins counts for all of them are showing 0%. Having investigated further I can see that the sample_values methods are never being called.


Is it the intention that when using Register field level covergoups that you MUST call the sample_values method manually after each Write or Read operation ?

I was sort of expecting that the hooks would all be there for the register field coverage to work in the same manner as the top level register block covergroup which did not require any manual call to its sample  method.




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I am already turning on coverage sampling by using the following in my test base class:


    // Register model
    // Enable all types of coverage available in the register model

    uvm_reg::include_coverage("*", UVM_CVR_ALL);


My understanding is that by specifying UVM_CVR_ALL, this should enable all field coverage which uses : UVM_CVR_FIELD_VALS

This seems to be true as the register field covergroups are being created,


The register block covergroup is also created and sampling is working fine at the top level...just not for the individual register covergroups.

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  • 8 months later...

I have the following:

  virtual function void build_phase(uvm_phase phase);
    uvm_reg_cvr_t   cov_type_result;
    uvm_reg::include_coverage("*", UVM_CVR_ALL);
    my_reg_block = my_reg_block::type_id::create("my_reg_block");    
    cov_type_result = my_reg_block.set_coverage(UVM_CVR_ALL);

    $display("cov_type_result     = %x", cov_type_result );



I believe this meets all of the requirements.

My register code is below: I see 'cg_vals' get created.  But sample_values is never called.


   class qsr_register_7 extends uvm_reg;

      uvm_reg_field RESERVED_QSR_07_31; // RESERVED
      rand uvm_reg_field ctl_pnld2_val; // PN31 seed for PN generator 2.

      // Function: coverage
      covergroup cg_vals;
         ctl_pnld2_val     : coverpoint ctl_pnld2_val.value[30:0];

      // Function: new
      function new(string name = "qsr_register_7");
         super.new(name, 32, build_coverage(UVM_CVR_FIELD_VALS));
            cg_vals = new();

      // Function: sample_values
      virtual function void sample_values();
         if (get_coverage(UVM_CVR_FIELD_VALS))

      // Function: build
      virtual function void build();
         RESERVED_QSR_07_31 = uvm_reg_field::type_id::create("RESERVED_QSR_07_31");
         ctl_pnld2_val = uvm_reg_field::type_id::create("ctl_pnld2_val");

         RESERVED_QSR_07_31.configure(this, 1, 31, "RO", 0, 1'b0, 1, 0, 0);
         ctl_pnld2_val.configure(this, 31, 0, "RW", 0, 31'b0000000000000000000000000000000, 1, 1, 0);


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  • 9 months later...
  • 3 weeks later...

i have a question regarding UVM registers coverage collection. The UVM register file is generated by the tool and by default in new function of the uvm register the coverage is OFF like below

 function new(string name = "temp_register");
  super.new(name, 32,build_coverage(UVM_NO_COVERAGE));
 endfunction: new

In build phase of my tb environment i have  coded like below:

  uvm_reg::include_coverage("*", UVM_CVR_ALL);

 reg_model = ral_block_temp_reg_file::type_id::create("reg_model", this);

i am unable to see the coverage collection for UVM register,register fields and address map in verification plan tree of vplan in Vmanager. 

Can any one help me in this ?

Thanks in advance.   http://www.traininginsholinganallur.in/php-training-in-chennai.html  |   http://www.traininginsholinganallur.in/pega-training-in-chennai.html

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  • 4 years later...

Finally (with a point in the right direction from Chris Spear) I found a solution to this that avoids having to manually call sample_values from my sequence, which I was never happy with.

In the register block, all of the your register definitions are extended from uvm_reg.

I manually added a new class to the register package  imp_cvr_reg   (for implicit coverage register), which extends from uvm_reg and defined a sample method which calls sample_values


class imp_cvr_reg extends uvm_reg;

  function new(string name="", int unsigned n_bits, int has_cvoerage);

         super.new, n_bits, has_coverage);


virtual function sample(uvm_reg_data_t    data,

                                           uvm_reg_data_t    byte_en,

                                           bit                           is_read,

                                           uvm_reg_map       map);



endclass : imp_cvr_reg


Then I changed all of my registers in my register block to extend from imp_cvr_reg

Then after a recompile, all of my register field coverage worked without the need to manually sample in my sequence

Even works when calling the built-in register sequences





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