zhiharev Posted June 9, 2014 Report Share Posted June 9, 2014 I have a sequencer: class l3_ack_sequencer #(type REQ = uvm_sequence_item) extends uvm_sequencer #(REQ); `uvm_component_utils_begin(l3_ack_sequencer#(REQ)) `uvm_component_utils_end uvm_analysis_imp #(REQ, l3_ack_sequencer) generate_res; function new (string name, uvm_component parent); super.new(name, parent); generate_res = new("generate_ack", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); endfunction // Generate ack virtual function void write(REQ item); endfunction endclass Then I declare a handle somewhere: l3_ack_sequencer #(core_l3q_ireq_tran) l3r_ireq; Using Synopsys VCS I have an error: Error-[iCTTFC] Incompatible complex type usage .../l3_ack_sequencer.sv, 33 Incompatible complex type usage in task or function call. The following expression is incompatible with the formal parameter of the function. The type of the actual is 'class $unit::l3_ack_sequencer#(class $unit::core_l3q_ireq_tran)', while the type of the formal is 'class $unit::l3_ack_sequencer#(class uvm_pkg::uvm_sequence_item)'. Expression: this Source info: uvm_analysis_imp_8::new("generate_ack", this) Can anyone help me to solve this problem or explain why it cant be solved? Quote Link to comment Share on other sites More sharing options...
apfitch Posted June 9, 2014 Report Share Posted June 9, 2014 I think you need `uvm_component_param_utils because you've got a parameter. Have a look for `uvm_component_param_utils in the documentation, regards Alan Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted June 9, 2014 Report Share Posted June 9, 2014 Alan's point is valid, you should use `uvm_component_param_utils to register parameterized components with the factory. I don't think this is the problem here however. Try changing this line: uvm_analysis_imp #(REQ, l3_ack_sequencer) generate_res; to this: uvm_analysis_imp #(REQ, l3_ack_sequencer #(REQ)) generate_res; because what you've declared is an aport that binds to a l3_ack_sequencer #(uvm_sequence_item) (the default value of REQ). Also, do you really need the parameterized sequencer? Do you plan on running multiple types of items on it? If not, then simplify your code by using a non-parameterized class: class l3_ack_sequencer extends uvm_sequencer #(core_l3q_ireq_trans); Quote Link to comment Share on other sites More sharing options...
zhiharev Posted June 10, 2014 Author Report Share Posted June 10, 2014 uvm_analysis_imp #(REQ, l3_ack_sequencer #(REQ)) generate_res; This solved the problem, thank you. I, really, forgot about declaring the parameter for the imp. Quote Link to comment Share on other sites More sharing options...
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