Running testcase in Questasim

[kirankumar2904]

Hi all,

    I tried to run a testcase ( test_write_sequence) using command line in Questasim... 

I had coded a AHB UVC and wanna to perform a simple write transaction.. 

But the tool called $finish in the uvm_root.svh file... Can anyone tell me how to fix this..

 

 

Log:

 

 

# --- UVM Report Summary ---

# 

# ** Report counts by severity

# UVM_INFO :    2

# UVM_WARNING :    2

# UVM_ERROR :    0

# UVM_FATAL :    0

# ** Report counts by id

# [RNTST]     1

# [TPRGED]     2

# [ahb_scoreboard]     1

# ** Note: $finish    : C:/questasim_10.0b/win32/../verilog_src/uvm-1.0p1/src/base/uvm_root.svh(392)

#    Time: 0 ns  Iteration: 196  Instance: /ahb_top

# 1

# Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.0b/win32/../verilog_src/uvm-1.0p1/src/base/uvm_root.svh line 392

 

 

[David Black]

You probably forgot to raise an objection in your run_phase as required by UVM.

 

Also, I suggest you use uvm-1.1d rather than 1.0p1 (very old version and has some "issues").

[kirankumar2904]

Hi,

    I have used task pre_body() and post_body() to raise and drop the objections,,, I will try to run the simulation using uvm-1.1d.. 

 

Thank you,

 

Regards,

Kiran Kumar