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Which one i use for verification both of systemC and UVM ?

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Hi

I willing to start verification.

But i'm not sure which i have to use method whether systemC scv or UVM.

Does anyone advice about what am i use and start from systemc or uvm for verification?

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Depends on what you are verifying, what you already have in place, what tools you own, and your expertise...

  • Do you have a SystemVerilog simulator available?
  • Are you verifying SystemC or an HDL (e.g. VHDL or SystemVerilog)?
  • Do you have knowledge of SystemVerilog OOP and/or UVM?

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