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Writing a System C wrapper for C++


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   Thanks for the reply.


  I have a C++ reference model to be used in UVM Environment.

MY approach was to wrap/call the C++ model in System C and connect it to System Verilog using ML_CONNECT.


the C++ model looks like this


void ex_top (int size, complex<double>* data_in, complex<double> * data_out))





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All you need is not only SystemC wrapper but ML-UVM wrapper also,  since I assume your C++ model is working on transaction level , you just need to register your port with ML-Library and create a replica of your seq_item in C++ and register the same with ML-UVM lib , on the UVM side connnect the analysis port with the ML-register_SC-export and through the transaction.


About SystemC registry, create a SC_MODULE and SC_CTOR to get register with SystemC Lib, rest functional call be used intact.

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