Muds Posted April 11, 2014 Report Share Posted April 11, 2014 Hi, How do we write a SystemC wrapper for a C++ class. Some examples would be useful. Quote Link to comment Share on other sites More sharing options...
David Black Posted April 11, 2014 Report Share Posted April 11, 2014 Errr... SystemC is C++. No wrapper needed. SystemC is not a new computer language. It is a library of classes and a methodology for modeling hardware. Not sure what you are really asking. Give an example of your C++ class and what you want to do with it. Quote Link to comment Share on other sites More sharing options...
Muds Posted April 15, 2014 Author Report Share Posted April 15, 2014 Hi, Thanks for the reply. I have a C++ reference model to be used in UVM Environment. MY approach was to wrap/call the C++ model in System C and connect it to System Verilog using ML_CONNECT. the C++ model looks like this void ex_top (int size, complex<double>* data_in, complex<double> * data_out)) { }; Quote Link to comment Share on other sites More sharing options...
Muds Posted April 15, 2014 Author Report Share Posted April 15, 2014 size - config input. data_in - Data input changes in every clock.. I would to buffer data at the input and output. Any suggestions would be helpful. thanks. Quote Link to comment Share on other sites More sharing options...
karandeep963 Posted April 16, 2014 Report Share Posted April 16, 2014 All you need is not only SystemC wrapper but ML-UVM wrapper also, since I assume your C++ model is working on transaction level , you just need to register your port with ML-Library and create a replica of your seq_item in C++ and register the same with ML-UVM lib , on the UVM side connnect the analysis port with the ML-register_SC-export and through the transaction. About SystemC registry, create a SC_MODULE and SC_CTOR to get register with SystemC Lib, rest functional call be used intact. Quote Link to comment Share on other sites More sharing options...
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