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  1. size - config input. data_in - Data input changes in every clock.. I would to buffer data at the input and output. Any suggestions would be helpful. thanks.
  2. Hi, Thanks for the reply. I have a C++ reference model to be used in UVM Environment. MY approach was to wrap/call the C++ model in System C and connect it to System Verilog using ML_CONNECT. the C++ model looks like this void ex_top (int size, complex<double>* data_in, complex<double> * data_out)) { };
  3. Hi, How do we write a SystemC wrapper for a C++ class. Some examples would be useful.
  4. Hi, We have a testbench in System Verilog which is uRM based. Please let me know if UVM supports module based metholdology? Is possible to convert from uRM to UVM with minimal changes?. Thanks Muds.
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