Which one is easier? RAL with irun or RGM with vcs.

[SeanChou]

All,

To make my UVM implementation executable with both Synopsys and Cadences' simulator. I need to choose one package.

1. Porting RGM to vcs, I tried and find some dpi header not found? is that impossible or someone already made it.

2. Porting VMM to UVM and make it executable with irun: any advice?

3. According to UVM 1.0 roadmap, register package spec. would be finalized on 8/30. would there be some hints for me to made this choice that I can fit into UVM1.0 Register Package with less effort.

Thanks for any suggestion!

[uwes]

hi sean,

uvmrgm is known to run on all three major ieee1800 simulators without any code changes. the only non-sv thing is that the backdoor access requires DPI (and VHPI in case VHDL is in the picture) (you have to include the dpi/*.c file which implements uvm_rgm_[set_hdl/release_hdl/get_hdl/backdoor_wait]). if you do not require backdoor access you can simply turn it off by "-define UVM_RGM_NO_BACKDOOR_DPI". the header files required to compile the c file should be part of your simulator.

>2. Porting VMM to UVM and make it executable with irun: any advice?

well porting the vmm library to uvm does not really make sense to me. if you really want to keep

your legacy code you might want to consider the uvm-vmm interoperability library. porting the non-uvm variant of

ral to ius is a non-trivial task as it also requires to fix the contents of the ral library in case its incompliant sv code or

IUS does not support yet.

3. the roadmap...

the plan of record right now is the following:

1. requirement collection/clarification has been completed

2. voting has completed on the requirements on "what has a high prio to be in uvm-10", "what is optional for uvm1.0"

3. right now

- register package vendors prepare a presentation/workshop of their package to the user community (see http://www.accellera.org/apps/org/workgroup/vip/event.php?event_id=2814)

- user/companies might review all proposed solutions to see if they meet their requirements

4. mid of sept2010 there will be an acellera face2face meeting where all proposals will be presented in depth with a followup voting on which package should be the starting point.

right now it is upto the accellera members to investigate if the proposed packages meets their requirements in terms of features, use models and scalability.

regards

/uwe

[SeanChou]

Thanks so much for the hint to disable the backdoor, it helps a lot to me. also hope later they could migrate to UVMRGM with less efforts.

[SeanChou]

After a quick test to disable the backdoor, there is another vcs error: Error-[ENUMASSIGNTYPE] Different enum type in assignment in

`uvm_blocking_put_imp_decl(_reg)

Cannot assign to variable of type 'uvm_pkg::uvm_port_type_e' a value of type '$unit::uvm_port_type_e' Source info:

\uvm_port_base#(uvm_tlm_if_base#(uvm_rgm_reg_op,uvm_rgm_reg_op)) ::new(name, imp, UVM_IMPLEMENTATION, 1, 1)

Use the static cast operator to convert the expression to the required enum type.

Would this need some modification of the UVM source code? Thanks!

[SeanChou]

After checking the problem was that I declared uvm_port_type_e again, it works on both simulators after remove the redundant declaration. thank you so much!