Tracing internal signals declared in sc_module using sc_trace

[viswanathb]

I have a sample systemc program wherein temp is declared as a sc_signal and the rest of the signals are declared as input/output ports.

SC_MODULE(clk_dut)

{

sc_in clk_in;

sc_in reset;

sc_out clk_out;

sc_signal temp;

In sc_main() i have instantiated submodules made connections and created the sc_trace file

sc_trace_file *fp;

fp=sc_create_vcd_trace_file("wave");

sc_trace(fp,clock1,"clk_in");

sc_trace(fp,t_reset,"reset");

sc_trace(fp,t_clk_out,"clk_out");

But how do i trace an internal signal 'temp' created in the dut module of the code using sc_trace() at sc_main().

Please help me with this at the earliest.

[manikanta.mashetti]

hi

 

In the sc_main(), you have to instantiate DUT module with some instance name use that instance name to trace the signal, like in your example only

 

clk_dut mod1("DUT");

...

...

sc_trace(fp,mod1.temp,"TEMP");

[David Black]

Manikanta's solution assumes temp is public. If not public, you can take the opposite approach and simply call sc_trace from within the module itself. You could even do it conditionally based on run-time command-line arguments:
  

sc_core::sc_trace_file trace_file = 0; //< initialize to indicate not open
top::before_end_of_elaboration() {
   for (int i=1; i<sc_argc(); ++i) {
      if ( trace_file == 0 && std::string(sc_core::sc_argv()[i]) == "-trace" ) trace_file = sc_core::sc_create_vcd_trace_file("your.vcd");
   }//endfor
}
top::end_of_simulation() {
   if ( trace_file != 0 ) sc_core::sc_close_trace_file(trace_file);
}
...
extern sc_core::sc_trace_file trace_file;
void dut::end_of_elaboration() {
   if (trace_file != 0) {
      sc_core::sc_trace(trace_file, temp,"temp");
   }
}

 
Of course I am assuming fp is made public as shown, and that you have opened it before end of elaboration:

[ANKUR SAINI]

@David Black: Hello David.. Nice solution.. just one comment.. as you mentioned the usage of callbacks -"before_end_of_elaboration" and "end_of_elaboration", I guess we can use the "start_of_simulation" and "end_of_simulation" also to do the same stuff you written in the code above.
Correct me if I am wrong anywhere.

[maehne]

3 hours ago, ANKUR SAINI said:

@David Black: Hello David.. Nice solution.. just one comment.. as you mentioned the usage of callbacks -"before_end_of_elaboration" and "end_of_elaboration", I guess we can use the "start_of_simulation" and "end_of_simulation" also to do the same stuff you written in the code above.
Correct me if I am wrong anywhere.

David's proposal is semantically very clear. The phasing of the before_end_of_elaboration(), end_of_elaboration(), and end_of_simulation() callbacks ensure that the actions to set up the tracing of implementation details are executed in the right order. IMHO, setting up tracing belongs semantically into the elaboration phase and not into the start of simulation. Then, you have to be aware that there is no guarantee in which order one type of callback is executed for all modules in your design. Therefore, you need to use two separate callbacks to open the trace file (before_end_of_elaboration()) and to register the signals for tracing (end_of_elaboration()).