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how to re-phaseing in the UVM

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Hi, experts,

Assume we have a dut can support difference configuration., and after each reset, and configure with different register, it can support different function. In some test cases, we want to test that it can safely transfer from mode A to mode B through reset or not. At mode A or mode B, we need difference UVC to feed stimulus. I want to know, how to do it in the current UVM method? DOes UVM support re-phasing from building again or any phase?

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Today, you cannot create new component objects after the elaboration phase is complete. So, do support what you want, I think you will need to have an agent that contains both uvcs, and put one of them in an inactive state until the mode changes. This, of course, assumes that the uvc has some way of turning its traffic generation off.

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Hi, Jlrose,

Thanks for your feedback. Your workaround works in some circumstance, but it is really complex to make these duplicated UVC in the verification env. I think the re-phaseing is important feature of verification enviornment .DO you know how can I submit the request the UVM organization?

Best Regards

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general phasing and custom phases have been a big point on the agenda in the last accellera face2face. there the companies agreed on the requirements and are now starting with the implementation and the implementation spec. here is some info about the new predefined phases


and here are the captured requirements for phasing model:




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I don't think this specific requirement is in the current phasing requirements. The ability to jump back phases is certainly there. But, as I understand your need, you want to be able to rebuild a part of your VE. This implies jumping all the way back to the build phase so and completely rebuilding based on some new information.

The phasing changes that have been discussed will likely make your life easier, but, as of now, they don't allow you to completely rebuild your environment (or sections of it).

The best thing you can do to effect the process is to attend the Acellera meetings. They are Weds mornings and are open to the public (of course, if you become a voting member of Acellera, then you have even more say).

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  • 2 weeks later...

Thanks to Umer and Jlrose,

I checked the accellera's discussion. The DAG phase suggestion and ability to roll back is good, though it can't statisfy me now. I think the test concatenation in the requirment maybe good to me. But not sure, whether it will implement in uvm1.0?

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