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Best Technique to Measure Simulation Times using VCS

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What is the best way to measure simulation time using VCS?


I would like to do some same-tool benchmarks to measure simulation performance improvements using different coding styles or tricks using the same simulator.


I do not intend to do cross-tool benchmarking; only same-tool benchmarking. I will check to see if techniques used with one tool also cause similar performance improvements across multiple tools, but I will not report actual speed differences between the tools (in accordance with my tool-usage agreements with multiple vendors).


I am trying to identify best performance coding practices.


The best technique I currently have is to do: "time simv"


This reports: real / user / sys times.


Regards - Cliff Cummings

Verilog & SystemVerilog Guru

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  • 1 month later...

hi Cliff,


VCS has a bunch of very advanced profilers built in for you to use.

like -reportstats -simprofile for memory and time along with constraints profilers.

Too many options and mechanism to list here.

RTFM I'm afraid.


Over the years we have been tweaking the profilers to give better info on what is good and bad for testbenches.

At some point we should compare notes on the topic.



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