plafratt Posted November 18, 2013 Report Share Posted November 18, 2013 I am learning about TLM to determine its feasibility for modeling component interfaces among modules that aren't modeled in SystemC. That is, I want to use TLM to model interfaces among components modeled with, say, C++ and/or VHDL. I want to be able to leave out sc_main and sc_start completely. Is TLM useful in such a context, or does it require the use of sc_main and sc_start? Thanks, Patrick Quote Link to comment Share on other sites More sharing options...
rajit.a Posted December 10, 2013 Report Share Posted December 10, 2013 HI patrick I have never heard of anyone using TLM without using sc_main or sc_start. You actually require a main file where you will either instantiate your top class or both initiator and target class.Here binding of sockets will be done. Regards Rajit Quote Link to comment Share on other sites More sharing options...
apfitch Posted December 12, 2013 Report Share Posted December 12, 2013 Hi Patrick, to a large extent "it's a tool issue". There are various ways of connecting SystemC and other languages in the tools. For instance you can leave out sc_main and mark the SystemC top level with a proprietary macro (the technique used in Questasim and Cadence). I can't remember the details in VCS or Riviera, but it's also possible. There's no standard way to communicate via TLM, but each vendor has some solution. Mentor have UVM Connect (which connects UVM to SystemC) - it is open-source, and should run on all UVM and SystemC compliant simulators - you can download it from Verification Academy. Synopsys have TLI, Cadence have UVMSC and variants. If you don't have UVM or SystemVerilog, you could create a SystemC TLM-to-pins adapter yourself (which would be straightforward for b_transport), and then instance the VHDL inside SystemC. Again the process of instancing the VHDL in the SystemC is proprietary, regards Alan Quote Link to comment Share on other sites More sharing options...
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