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TLM without SystemC

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I am learning about TLM to determine its feasibility for modeling component interfaces among modules that aren't modeled in SystemC. That is, I want to use TLM to model interfaces among components modeled with, say, C++ and/or VHDL.  I want to be able to leave out sc_main and sc_start completely. Is TLM useful in such a context, or does it require the use of sc_main and sc_start?




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  • 3 weeks later...

Hi Patrick,

  to a large extent "it's a tool issue". There are various ways of connecting SystemC and other languages in the tools. For instance you can leave out sc_main and mark the SystemC top level with a proprietary macro (the technique used in Questasim and Cadence). I can't remember the details in VCS or Riviera, but it's also possible.


There's no standard way to communicate via TLM, but each vendor has some solution. Mentor have UVM Connect (which connects UVM to SystemC)  - it is open-source, and should run on all UVM and SystemC compliant simulators - you can download it from Verification Academy. Synopsys have TLI, Cadence have UVMSC and variants. 


If you don't have UVM or SystemVerilog, you could create a SystemC TLM-to-pins adapter yourself (which would be straightforward for b_transport), and then instance the VHDL inside SystemC. Again the process of instancing the VHDL in the SystemC is proprietary,




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