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Everything posted by plafratt

  1. Thank you for the helpful response. I believe I need to think this over a little more. I am still not entirely clear on how the arbiter should handle the case where one of the input threads may not check in during a given arbitration cycle, as the arbiter cannot make its arbitration decision until it is sure that all of the input threads that will check in have done so.
  2. I am facing a dilemma with the scheduling of SystemC processes. I have a feeling it is because I have erred in my design approach and wanted to see if someone could offer some guidance. Say that you have a SystemC thread that arbitrates transactions that arrive through multiple FIFOs. The threads that enqueue the transactions into the FIFOs are untimed. When a request arrives at an input FIFO of the arbiter, the arbiter gets notified. At this point, the arbiter does not know which of the FIFOs will eventually get a transaction in it at this time stamp. We'd like to wait until all of the other threads have executed before the arbiter proceeds to make its arbitration decision. As I understand, one way to do this would be just to make a bunch of wait(SC_ZERO_TIME) calls. But this seems a bit like a hack, for various reasons (e.g., what if later, there are more untimed processes added upstream from the input threads? Then the arbiter has to add more wait(SC_ZERO_TIME) calls to account for these). I am wondering if this would just be considered a bad design. Since real hardware takes time for activity to occur, perhaps this is not the intended use of the delta scheduling in SystemC. Or, maybe I am just approaching this in the wrong way? Any help is appreciated.
  3. Great, thank you. I was aware of ok_to_put(), but I think I had some confusion about how to use it in my situation. It looks like it should do what I need. Thanks!
  4. Well, I'm not sure something like deque will provide what is needed, because I still need process notifications when an entry is written or read. I think what I am not seeing is how to write into the fifo and then block the writer until the reader reads from it. I can write something custom based on deque or something else (or look for another class in sc_core or tlm) to provide this, but wanted to be sure that tlm_fifo didn't provide this first.
  5. I am using a tlm_fifo. When I put() into it and then immediately call nb_can_get(), it is returning false. Is this an invalid use of the tlm_fifo to call put() and nb_can_get() in the same delta? Or, have I made a mistake somewhere?
  6. I see now that the TLM2.0 LRM explicitly disallows this. (In the version of the LRM I have, this is in the section " The phase argument".) However, this text there does refer to the "base protocol." So, perhaps the way to allow what I am trying to do would be to define a new protocol. Any input on this is appreciated, though, in case that is the wrong way to go about this.
  7. With TLM2.0 nb_transport, is there a way for an initiator to tell an interconnect that it wants to preempt the last request the initiator sent? For example, say that the interconnect can buffer only 1 request. The initiator sends a low priority request R0 to the interconnect. Some time passes, and the initiator begins another, higher priority request R1. The initiator knows that the interconnect hasn't serviced R0 yet, because the initiator hasn't received a response for R0 yet. The initiator wants to tell the interconnect, "Throw out R0 and use R1 instead." I can achieve this by just having the initiator send R1 to the interconnect, and then having it send R0 again at a later time (after R1 is done being serviced). However, it isn't clear to me that TLM2.0 protocol allows the initiator to send R0 an arbitrary number of times in the BEGIN_REQ phase.
  8. Thank you for the thoughts. I am using acquire() and release() to ensure that the memory is safe while I am using the transaction in the target. The specific problem I am facing is that the initiator might call, for example, set_address() on the transaction after it receives the response, while the target is still using it. The target needs access to the original address.
  9. In systems where a target can send an early response, such as a posted write, and the initiator can change the transaction after it receives the response, how do most developers handle the transaction in the target while avoiding seeing the initiator's changes to that transaction? An obvious solution is for the target to do a deep copy of the transaction, but in a complex system with many modules, having each module potentially create its own copy of each transaction can make debug and performance analysis difficult. Another option is for the target to save the relevant information from the transaction in an extension when the target receives that transaction, but this has the problem that the developers of the target must always remember to use the accessors in the extension, rather than the standard ones for the transaction.
  10. Thank you for the responses. Sorry for the delay in my response. I'd gotten busy, and I am just now getting around to signing back in. We don't seem to be having this issue anymore. I am not sure if it because of code updates or because of a compiler upgrade. We recently switched from g++ 4.9.2 to 6.2.1, so that may have resolved the issue. The path in question is sc_fifo::read() -> sc_fifo::read(T& val_) -> sc_fifo<T>::buf_read( T& val_ ). On line 410, buf_read() returns false without setting val. None of the functions in the call chain set val, so when the original call to sc_fifo::read() returns, it is returning its locally-declared tmp variable, which was passed to sc_fifo::read(T& val), which never sets val. As I mentioned, though, this doesn't seem to be causing a problem for us at the moment. It may have been a compiler issue that got resolved when we upgraded. Thank You and Regards, Patrick
  11. I get the warning when building my code that uses sc_fifo.h, not when building systemc. I assume this is because the function is declared inline.
  12. For sc_fifo::read(), some versions of g++ give me a warning that the variable tmp is unset. I see there is a path through read() that leaves tmp unset, but I don't think it is possible that this path ever gets executed. Is there a way around this warning that doesn't require disabling the warning in g++ or changing sc_fifo.h?
  13. That is it. Thank you very much. Regards, Patrick
  14. I looked at the implementation of sc_fifo, as I'd guessed that in the read() function, it would just notify data_read_event, but the logic surrounding the notify looks a little more complex than that.
  15. I'm actually using read(), rather than nb_read(). Given the specification you posted, it seems like something unexpected is happening. I can see the fifo is getting read (I put a log statement in after the read() call), but I don't see the thread that is waiting on data_read_event getting woken up (I put a log statement there, too). The thread that is waiting on data_read_event does eventually get woken up when the last item is read off the fifo.
  16. I had been using the sc_fifo with the assumption that data_read_event would get notified whenever the receiver read from the fifo. However, I am seeing cases where the receiver reads from the fifo, but the data_read_event doesn't get notified. Is this the intended behavior?
  17. Is there a preferred way of adding an event to the static sensitivity list for a single wait? I think it would be possible by ORing the static sensitivity list with another event, and sending the result to a wait. The problem is that I don't see an accessor function for a thread's sensitivity list. I guess one approach is to hard-code an sc_event_or_list that includes the static sensitivity list, but that seems a little clunky. sc_event_or_list or_list; for (int i=0; i< 100; i++) or_list |= my_array_of_100_events; or_list |= new_event; wait( or_list ); Is there a better way to add an event to the sensitivity list for a single wait? Thanks, Patrick
  18. Philipp, Thanks for the response. This is very helpful. This makes sense now. I had noticed the use of the dereference operator, and it had caught my attention since the initiator_socket hadn't been declared as a pointer. But it didn't occur to me to look into that further. I think perhaps I was too distracted with my search through the inheritance hierarchy. Thanks again, Patrick
  19. I am a bit confused by the usage of the b_transport function in the file examples/tlm/common/src/lt_initiator.cpp. The lt_initiator class has a simple_socket_initiator member that is calling the b_transport function, and I’m trying to figure out how the simple_socket_initiator class is getting access to this function. The only connection in the inheritance hierarchy I’ve been able to find between simple_socket_initiator and the b_transport function is a distant link through a friend declaration in the tlm_base_target_initiator class. I’ve drawn a diagram showing this connection. This diagram is attached. I could be wrong, but I don’t think that this connection would allow the simple_socket_initiator to access b_transport. I am lead to the conclusion that I think there is some other connection between simple_socket_initiator and b_transport that I am not seeing. At runtime, simple_socket_initiator’s b_transport function call is getting resolved to simple_target_socket’s implementation. I’m just not sure how this resolution is happening. Any help anyone can offer is appreciated.
  20. I just found this discussion on this topic, which was very helpful. However, any additional thoughts that anyone might have on the topic are appreciated.
  21. Hello, In my previous modelling efforts with SystemC, I have, in general, used SystemC FIFOs for communication in abstract models. I have learned the basics of TLM and gone through a couple of examples, but it isn't clear to me what the advantages are of TLM over FIFOs. Someone has explained to me that there are performance advantages of TLM. However, for my purposes, I am not so concerned with performance. Does anyone have a reference that presents the advantages of TLM over more conventional communication mechanisms in SystemC? Any help is appreciated. Thanks, Patrick
  22. Jens, Sumit- I haven't tried what Jens has proposed with OpenMP, so I can't speak from experience. However, my understanding is that Jens is perhaps not trying to parallelize a single call to sc_main, but rather trying something akin to creating multiple processes, each from its own sc_main. If each sc_main is isolated from the others, perhaps each could have its own elaboration. This seems to me like something that might be feasible. However, I would not think that SystemC's internal processes (i.e. sc_methods, sc_threads, etc.) could be synchronized across processes in such an environment. Regards, Patrick
  23. I am learning about TLM to determine its feasibility for modeling component interfaces among modules that aren't modeled in SystemC. That is, I want to use TLM to model interfaces among components modeled with, say, C++ and/or VHDL. I want to be able to leave out sc_main and sc_start completely. Is TLM useful in such a context, or does it require the use of sc_main and sc_start? Thanks, Patrick
  24. Thank you for the responses, everyone. This is quite helpful. I will keep an eye out for ongoing efforts to parallelize SystemC. Regards, Patrick
  25. I am interested in learning whether SystemC supports parallel simulation - that is, utilizing multicore processor or multiprocessor systems to speed up simulations. I see in the SystemC 2.1 Features document the specification of a function sc_spawn. Does this function spawn an new Linux process? Near the end of the Features document, there is mention of thread support based on Posix threads. Does building SystemC with pthreads enabled allow for multi-threaded simulations? If so, is a thread created for each SC_THREAD and SC_METHOD, or is some other approach used? Any help is appreciated. Patrick
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