A module with a delayed output

[srahulkumar1989]

Hi all,

      i am trying to translate a simulink model to system c module. The simulink block is a source block where it generates random number in the range of [ 0 , 253 ] and with a explicit sample period( the block produces outputs and if appropriate, updates its internal state) of 9 ns, and the output of this block is given to the next block with a latency of 1 sample period.

 

i tried to translate this block to a system c module as shown below:

 

 

#include "systemc.h"
#include <stdlib.h>  //for srand(uint) and rand()

SC_MODULE(RNG){
sc_in_clk clk;
sc_out< sc_uint > output;

sc_uint  A;

void process(){    //

while(true)
{
wait(9, SC_NS); // Timed sampling, based on simulink block sample time

A=rand() % 254 ; // do the process

wait(9, SC_NS); // delaying the output for 1 latency ie. 1 sample period 

output.write(A);   // then write the output

}
}

SC_CTOR(RNG)
{
SC_THREAD(process);
sensitive<< clk.pos();
}
 

 

 

will the above code imitates the simulink model with its specifications as i prescribed? please have a look and let me know how i can proceed for the solution.

 

Thank you.

[ralph.goergen]

Hi. 

 

Hard to say, but I think it doesn't. I need more information. 

 

What is your sample period in Simulink?

Why do you have two wait statements in the process?

Why is your process sensitive to clk when you wait for time?

 

 

If I understood you right, you want to model a block that produces a new value every 9 ns. 

Your process generates a new value every 18 ns (9+9).

 

If you want to delay each output value by one Simulink sample period, you can use a delay or memory block in Simulink. 

If you want to delay each value by 9 ns in SystemC you can use an intermediate signal and a second process. Or you just start 9 ns later (start the process with wait, then rand+ write). 

 

The exact time, when the value appears in Simulink depends on your co-simulaiton infrastructure. 

In your process, the first rand value is written to the outport after 18 ns. I.e. it appears at the 'other end of the signal' after 18 ns + 1 delta. In Simulink, there is no delta. Hence it is your interpretation of time whether 18 ns + 1 delta is still 18 ns in Simulink or later than 18 ns. 

 

Greetings

Ralph

[srahulkumar1989]

Dear Mr. Ralph,

 

Thank you for the reply and interaction.

 

my simulink random generator block sample period is 9 ns and the output of this block is given to a delay block with latency 1 sample period(9ns) and then it is given to the next functional block.

 

So i want to write a RNG systemC module which produces new value every 9ns and write the outputs at the outport after a delay of 1 sample period (9ns).

As you have mentioned  :

 you just start 9 ns later (start the process with wait, then rand+ write).

is that mean i just start the process with wait(9, SC_NS) ?  could you please explain this point little more detailed.

 

Thank you

[ralph.goergen]

Hi. 

 

What you want is: 

 

RNG-intern (generation)
 1 2 3 4 5 
RNG-out
   1 2 3 4 5 
 

To achieve this, you can do something like: 

sc_signal s1;
process1: (no static sensitivity)
{
  while(true){
    wait(9ns);
    s1.write(rand);
  }
}

process2: (no static sensitivity)
{
  sc_uint tmp;
  wait(s1.value_change_event());
  tmp = s1.read();
  while(true){
    wait(9ns or s1.value_change_event()); 
    out.write(tmp);
    tmp = s1.read();
  }
}

 

But for another component watching the output, this is the same as: 

RNG-intern (generation)
   1 2 3 4 5 
RNG-out
   1 2 3 4 5 

Hence , you can use: 

p1()
{  
  wait(9ns);
  while(true)
  {
    wait(9ns);
    out.write(rand);
  }
}

Greetings

Ralph

[srahulkumar1989]

Dear Mr. Ralph,

 

 Yes its clear now we should use a intermediate signal if we want to delay each of the value by 9ns and use a second process, or can just start the process 9ns later with wait(9, SC_NS).

 

and thanks for warning me about delta cycle semantics of a signal in systemc in connection with simulink simulation semantics, I have to take a look about the infrastructure and continue with the translation.

 

Thanks for your interaction.

[maehne]

I would like to add that the TDF model of computation of SystemC AMS has semantics very close to Simulink. It is multirate capable and allows you to express sample delays, which are an integer multiple of the sampling period, directly on the input/output port of each module. Also its multi rate capabilities facilitate the modeling of DSP algorithms in SystemC. In addition, the model execution is accelerated due to the static scheduling of the execution of TDF modules' processing member function in a cluster of connected modules.

 

Therefore, I suggest you to have a look on the SystemC AMS User's Guide available from <http://www.accellera.org/>, whether it may fulfill your needs better.