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  1. Thanks Mr. Alan for the response. i have tried to know about range method by a simple code . variable.range(4,0) will reprensent the bottom 5 bits and discard the remaining 3 bits of a 8 bit input. variable.range(7,5) will discard the bottom 5 bits and represent the remaining 3 bits of a 8 bit input. please correct me if i am wrong.
  2. Hello all, I have just started the practical implementations in systemC. Here i am trying to implement a paradigm of Bit slicing in systemC. Like: My input is a 8 bit unsignedint type which should be sliced and the output to be a 2 bit unsignedint type. Here i am trying to slice the bits with some conditions - bottom bit of slice - offset by 0 - Relative to LSB Overall - slicing from bit 0 to bit 5 of a 8 bit input. #include "systemc.h" SC_MODULE(slice){ sc_in<sc_uint< 8,8> > input; sc_out<sc_uint< 2,2> > output; void do_slice(){ // s
  3. Thanks for the response Philipp. I tried to figure out what was the problem in my code. I used a source file (.cpp file) to instantiate the rand module and its connections . So, when i defined SC_INCLUDE_FX in the main file also, the error was solved. So i understood that we need to define the macros related to fixed point types in the related cpp files also
  4. Hi all, I am working with sc_fixed point types in systemc and i tried a small code with the usage of fixedpoint types. #define SC_INCLUDE_FX #include "systemc.h" #include <stdlib.h> //for srand() and rand() SC_MODULE(rand){ sc_out<sc_ufixed<8,8,SC_TRN,SC_SAT> > output; sc_ufixed<8,8,SC_TRN,SC_SAT> A; void process(){ while(true) { wait(19, SC_NS); A=rand() % 254 ; // range 0 to 253 output.write(A); } } SC_CTOR(rand) { SC_THREAD(process); } }; The above code is just a source module which provides the rand numbers in the fixed point format to the n
  5. Dear Mr. Ralph, Yes its clear now we should use a intermediate signal if we want to delay each of the value by 9ns and use a second process, or can just start the process 9ns later with wait(9, SC_NS). and thanks for warning me about delta cycle semantics of a signal in systemc in connection with simulink simulation semantics, I have to take a look about the infrastructure and continue with the translation. Thanks for your interaction.
  6. Dear Mr. Ralph, Thank you for the reply and interaction. my simulink random generator block sample period is 9 ns and the output of this block is given to a delay block with latency 1 sample period(9ns) and then it is given to the next functional block. So i want to write a RNG systemC module which produces new value every 9ns and write the outputs at the outport after a delay of 1 sample period (9ns). As you have mentioned : is that mean i just start the process with wait(9, SC_NS) ? could you please explain this point little more detailed. Thank you
  7. Hi all, i am trying to translate a simulink model to system c module. The simulink block is a source block where it generates random number in the range of [ 0 , 253 ] and with a explicit sample period( the block produces outputs and if appropriate, updates its internal state) of 9 ns, and the output of this block is given to the next block with a latency of 1 sample period. i tried to translate this block to a system c module as shown below: #include "systemc.h" #include <stdlib.h> //for srand(uint) and rand() SC_MODULE(RNG){ sc_in_clk clk; sc_out< sc_uint > o
  8. Thank you for your reply Torsten. I can understand .to_bool () member function cannot be used with fixed point types and fixed point types must be provided with the read member functions to read the value and also a criterion should be provided for outputting the boolean value (1 or 0) keeping the things on mind i tried to rewrite the code for an example. Please check the code and correct me if i am wrong. #include "systemc.h" #define SC_INCLUDE_FX SC_MODULE( convert) { sc_in<sc_ufixed < 12, 12, SC_TRN, SC_SAT > > count; sc_out<bool > FIFO_we; void funct
  9. Is my question clearly understandable? if not please let me know!
  10. Hi all, I am newbie to system c and i am trying to work on system c data type's conversions. I have a inport which a system c ufixed type and i need to change it to a bool type on the outport. i tried the following code. SC_MODULE(convert) { sc_in<sc_ufixed < 1, 1, SC_TRN, SC_SAT > > din; sc_out<bool> dout; bool i; void conversion1() { i = din.to_bool(); dout.write(i); } SC_CTOR(convert) { SC_METHOD(conversion); sensitive<< din; } }; Is the above code correct? do i need to use the process method to convert the inport type to a another
  11. Hello Mr. Ralph, Thank you very much for your reply, as you said i will have to look upon the timing semantics and its related stuff while transferring a simulink to SystemC model, and will go through heirarchial design too. Regarding the design: Do i need connect the outport of module M1 to the inport of the model M2 through a signal S and make the process in M2 sensitive to the inport of Module M2. so that whenever the output changes in M1, the input of M2 changes and the process activates. Am i correct? please let me know whether i have the correct understanding
  12. Hi all, I am new to the system C and just had learnt about theoretical concepts in systemC. Currently i am trying to translate a simulink model to a systemC model and i have some doubts when i am trying to do. Please refer the below attached simulink model, a counter block is present and the output of the counter block is given as input to the successive block. my doubt is how to send the data from this block to next block . As soon as the count value is increased by 1 it should send the data to the next block and the next block works according to the count value. i tried som
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