ofird Posted September 15, 2013 Report Share Posted September 15, 2013 Hi, Assuming my DUT has 2 external CPU interfaces that can access to the same Register Model. How should I implement it in my UVM environment ? I guess I need 2 adapters and 2 predictors. Do I need to set 2 maps ? one per sequencer ? Is it possible to set 2 different sequencers to the same map ? or we have to set 2 maps and set_sequencer to each one of them ? Thanks, Ofir Quote Link to comment Share on other sites More sharing options...
apfitch Posted September 15, 2013 Report Share Posted September 15, 2013 The talk by Steve Holloway at DVClub Bristol recently has some information about multiple address maps, i.e. a single set of registers accessed via 2 interfaces. Steve's example talks about 2 different IPs, but I think it's relevant to your problem. The presentation is here: http://testandverification.com/DVClub/09_Sep_2013/DVClub-UVMRegistersAdvanced_Topics-SteveHolloway.pdf and accessible from here: http://testandverification.com/publications/published-articles/dvclub/dvclub-on-9th-september-2013/steve-holloway-dialog-semiconductors/ regards Alan Quote Link to comment Share on other sites More sharing options...
uwes Posted September 16, 2013 Report Share Posted September 16, 2013 hi, this is a known issue: http://eda.org/svdb/view.php?id=4497 http://eda.org/svdb/view.php?id=4009 http://eda.org/svdb/view.php?id=4305 http://eda.org/svdb/view.php?id=3369 the workaround today is to have another map instance having the same register set added as the original map. /uwe Quote Link to comment Share on other sites More sharing options...
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