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Multiple CPU interfaces can access the same register model

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Assuming my DUT has 2 external CPU interfaces that can access to the same Register Model.

How should I implement it in my UVM environment ?


I guess I need 2 adapters and 2 predictors. Do I need to set 2 maps ? one per sequencer ?

Is it possible to set 2 different sequencers to the same map ? or we have to set 2 maps and set_sequencer to each one of them ?


Thanks, Ofir

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The talk by Steve Holloway at DVClub Bristol recently has some information about multiple address maps, i.e. a single set of registers accessed via 2 interfaces. Steve's example talks about 2 different IPs, but I think it's relevant to your problem. The presentation is here:




and accessible from here: http://testandverification.com/publications/published-articles/dvclub/dvclub-on-9th-september-2013/steve-holloway-dialog-semiconductors/




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