ofird Posted September 15, 2013 Report Share Posted September 15, 2013 Hi, Assuming my DUT has 2 external CPU interfaces that can access to the same Register Model. How should I implement it in my UVM environment ? I guess I need 2 adapters and 2 predictors. Do I need to set 2 maps ? one per sequencer ? Is it possible to set 2 different sequencers to the same map ? or we have to set 2 maps and set_sequencer to each one of them ? Thanks, Ofir Quote Link to comment Share on other sites More sharing options...
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