VCS: uvm config db with array of interface

[fbochud]

Hi,

 

Is there limitations when using uvm_config_db with interface array:

 

Here is an example where I get compilation error:

 

module tb_top();

   import uvm_pkg::*;

   /* DUT interfaces */
   test_if #(.MY_PARAM(4)) my_if   [3] (); // array of interfaces

 

   // Clocks and resets

   [...]

   // design under verification
   [...]

   initial begin
     string inst_name;

      for (int i = 0; i < 3; i++) begin
         $sformat(inst_name, "*.source[%0d].*",i);
         uvm_config_db#(virtual test_if#(.MY_PARAM(4)))::set(uvm_root::get(), inst_name, "vif", my_if); // This line gives compilation error !!!
      end

      run_test();
      $finish;
  end

endmodule
 

Compilation error:

 

Identifier 'my_if' has not been declared yet. If this error is  not expected, please check if you have set `default_nettype to none.

 

 

Is that a simulator issue or is that not supported at all?

Thank you

 

Florian

 

 

[getvictor]

I was able to compile with the following line modified:

virtual test_if #(.MY_PARAM(4)) my_if [3]; // array of interfaces

Complete code and compile results on EDA Playground: http://www.edaplayground.com/s/4/118  

[fbochud]

If I use a virtual interface, I get the following error (with VCS 2013):

 

Error-[NYI] Not Yet Implemented
[...]/tb_top.sv, l.xx
  Feature is not yet supported: xmr "my_if[0].reset" containing
  virtual interface "my_if" is passed at port at MX boundary.

 

On http://www.edaplayground.com/s/4/118 (very nice site, btw), I get it to compile with Questasim. So, VCS team, any plan to support this?

 

Another related question:

- how would the instantiation look like if the interface would be like:

 

interface test_if #(int MY_PARAM=4) (input bit clk);
   logic reset;
endinterface : test_if

 

module tb_top();

 

   logic [3] main_clk_array;

   virtual test_if #(.MY_PARAM(4)) my_if [3] (main_clk_array); // array of interfaces, how to I assign main_clk_array to the interface? Is main_clk_array[0] assigned to my_if[0].clk?

 

   [...]

 

endmodule;

[logie]

You need to instantiate an array of interfaces and not "virtual interfaces".   I am assuming that you have an array of intefaces that you are trying to connect to an array of VIP masters/slaves.     Your original code instantiating array of interfaces is correct.

 

The problem appears  to be resolving  the my_if  instance handle in the uvm_config_db::set() call.

 

Try the following: 

 

uvm_config_db#(virtual test_if#(.MY_PARAM(4)))::set(uvm_root::get(), inst_name, "vif", tb_top.my_if);

 

 

By the way, I dont have access to VCS. So let me know if this fixes your problem.

[fbochud]

Logie, thank you for your comment, it almost worked and gave me a better error (it didn't like non-constant arg from my previous inner for loop).

It now compiles by using a generate loop around the uvm_config_db

 

genvar i;

for (i=0 ; i < 3 ; i++)
     begin
        initial begin
           string inst_name;

           $sformat(inst_name, "*.source[%0d].*",i);
           uvm_config_db#(virtual test_if #(.G_NUM_PAR_CHANNELS(4)))::set(uvm_root::get(),
                                                                                 inst_name,
                                                                                 "vif",
                                                                                 my_if);
        end
   end

 

 

Any ideas about the related issue?

 

Another related question:

- how would the instantiation look like if the interface would be like:

 

interface test_if #(int MY_PARAM=4) (input bit clk);
   logic reset;
endinterface : test_if

 

module tb_top();

 

   logic [3] main_clk_array;

   virtual test_if #(.MY_PARAM(4)) my_if [3] (main_clk_array); // array of interfaces, how to I assign main_clk_array to the interface? Is main_clk_array[0] assigned to my_if[0].clk?

 

   [...]

 

endmodule;

[logie]

Yes. I would expect the my_if[0] input clk to be connected to the main_clk_array[0].   Are you seeing something else?

 

By the way, since you are going with generates for the uvm_config_db call, you may also want to consider generates

around the instantiation of the interface itself (instead of using array of interfaces).   This might make your code a little

simpler.  Here is a possible solution, with generates around the instantiation and the config_db::set().

 

 

module tb_top();

      import uvm_pkg::*;

 

      genvar i;

      generate

              for( i = 0; i < 3; i++)  begin : r_loop

 

                    test_if #(.MY_PARAM(4)) my_if ();

                    initial begin

                          $sformat(inst_name, "*.source[%0d].*",i);

                          uvm_config_db#(virtual test_if#(.MY_PARAM(4)))::set(uvm_root::get(), inst_name, "vif", my_if);

                    end

             end

      endgenerate

 

　

       // run_test();

       

endmodule

[fbochud]

Thank you Logie.

In your last suggestion, how would I access my_if outside the generate loop? The dut instantiation is connecting to the different my_if.

[logie]

The instance names should be

  tb_top.r_loop[0].my_if

  tb_top.r_loop[1].my_if   and so on.

 

Note that r_loop is used as a label in the generate loop.