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Everything posted by getvictor

  1. qinhailiang, Are you asking when you can get UVM 1.2? UVM is open source, so you can grab the latest code any time. Here is the UVM 1.2 RC3: http://sourceforge.net/p/uvm/code/ci/UVM_1_2_RELEASE_RC3_WITHHTMLDOC/tree/distrib/ Once Accellera puts its stamp of approval, you'll be able to download it from accellera.org
  2. Recently I added SystemC support to EDA Playground. Now it is possible to run SystemC simulations from your web browser (including viewing waves) without installing anything. Here is a SystemC counter design and testbench example 1. Would this be useful for SystemC students and users (for sharing examples and best practices, prototyping, etc.)? 2. Anyone interested in creating additional examples or web-based hands-on tutorials? For reference, here is a short YouTube intro: Run C++ and SystemC in Your Web Browser
  3. The first video series Introducing What's New in UVM 1.2 is out. Also, here is the UVM 1.2 Class Reference This video series covers the changes and new features introduced in UVM 1.2. It is intended for engineers who are already somewhat familiar with UVM. The series comes with CODE EXAMPLES THAT WORK. That's right, real working code and not just a snippet on a slide. The series has the following parts, covering different areas of UVM 1.2 changes. Recommend viewing in 720p quality or higher. uvm_object must have constructor code example Config DB uvm_enum_wrapper code example set_config code example Objections objections code example set_automatic_phase_objection code example Sequences sequence code example uvm_integral_t type uvm_integral_t code example Reporting (major changes) reporting code example Phasing phasing code example Factory extending factory code example parametrized uvm_event uvm_event code example Transaction recording (coming soon) I hope you find it useful. Let me know what other topics you'd like to see. Note: The videos are based on UVM 1.2 release candidate. I do not expect the features covered in the series to change for the final release. The above code examples will always work. If needed, they will be updated for the final UVM 1.2 release.
  4. uwe, I tried `uvm_error_context and it works: http://www.edaplayground.com/s/4/839 `uvm_error_context("ID", "Something failed", uvm_root::get());
  5. George, We need to see more of the code to help you. Can you put up a snippet on EDA Playground? For reference, here is a simple ModelSim UVM testbench
  6. What is the recommended way to call UVM report functions and macros from a static method in a uvm_component? Having the following code: static function static_check(); `uvm_error("ID", "Something failed"); endfunction causes a compile error: ** Error: testbench.sv(15): (vlog-2888) Illegal to access non-static method 'uvm_report_enabled' from a static method. Full example can be edited and run here: http://www.edaplayground.com/s/4/762
  7. I need to dump the contents of a queue in my scoreboard. When the queue is large and the items in the queue have a lot of properties, the report becomes very large and hard to parse. This is because the default UVM print format is table. foreach(my_q[i]) begin `uvm_info("REPORT", $sformatf("my_q[%0d]:\n%s", i, my_q[i].sprint()), UVM_LOW) end I'm interested in printing each item on a single line. How do I accomplish the following: Change the format from the command line? Change the default format that is used by my whole scoreboard? Change the format that is used only by the method that is dumping the queue contents? You can edit and re-run the simple example of this issue here: http://www.edaplayground.com/s/4/656
  8. Your can edit and simulate a simple SystemVerilog design and UVM testbench on EDA Playground: http://www.edaplayground.com/s/example/546 No software installation needed. About EDA Playground: EDA Playground is a web browser-based integrated development environment (IDE) for simulation of SystemVerilog, Verilog, VHDL, and other HDLs. EDA Playground is a free web application that allows users to edit, simulate, share, synthesize, and view waves for hardware description language (HDL) code. It is the first online HDL development environment and waveform viewer for the semiconductor industry. EDA Playground homepage: http://www.edaplayground.com Engineers have used EDA Playground for: -- creating hands-on training for students -- demonstrating best practices to other engineers -- asking SystemVerilog questions on online forums -- testing candidates' coding skills during technical interviews (phone and in-person) -- quick prototyping -- trying something before inserting the code into a large code base -- checking whether their RTL syntax/code is synthesizable EDA Playground is actively seeking partners to integrate additional EDA tools. Future tools will include formal verification, linting, and analog and mixed-signal support.
  9. Update: EDA Playground now supports SystemVerilog and UVM. You can edit and simulate this simple UVM testbench: http://www.edaplayground.com/s/example/546
  10. I was able to compile with the following line modified: virtual test_if #(.MY_PARAM(4)) my_if [3]; // array of interfaces Complete code and compile results on EDA Playground: http://www.edaplayground.com/s/4/118
  11. Take a look at this thread: http://forums.accellera.org/topic/1277-free-systemveriloguvm-simulator-for-small-amounts-of-code-exists/
  12. There is a free browser based IDE for Verilog and SystemVerilog called EDA Playground. It is specifically designed for small prototypes and examples. Currently, SystemVerilog support is limited to a few features, such as packages: http://www.edaplayground.com/s/4/26 EDA Playground is currently seeking a partner to offer limited public access for UVM simulations. That said, UVM is fully supported for private deployments. Here is UVM code with sim results: http://www.edaplayground.com/s/4/64
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