santhoshvlsi Posted May 17, 2013 Report Share Posted May 17, 2013 # ** Error: (vsim-3601) Iteration limit reached at time 530 ns.# This is a zero-delay loop i am running the test case in UVM to verify the core. The core have accumulator,instruction decoder and ALU.The ALU is getting the first data only. While coming to second the instruction , the simulator is getting the error like thisSimulator :model sim # ** Error: (vsim-3601) Iteration limit reached at time 530 ns.# This is a zero-delay loop: Please suggest me about this issue to rectify......... Quote Link to comment Share on other sites More sharing options...
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