Zero delay loop in verilog design

[santhoshvlsi]

 

# ** Error: (vsim-3601) Iteration limit reached at time 530 ns.
# This is a zero-delay loop

i am running the test case in UVM to verify the core.

The core have accumulator,instruction decoder and ALU.
The ALU is getting the first data only. While coming to second the instruction , the simulator is getting the error like this
Simulator :model sim

# ** Error: (vsim-3601) Iteration limit reached at time 530 ns.
# This is a zero-delay loop:

Please suggest me about this issue to rectify.........

[dave_59]

The answer is the same as what I posted here: https://forum.verificationacademy.com/forum/verification-methodology-discussion-forum/uvm-forum/30592-zero-delay-loop-verilog-design#comment-30597