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eclipse Waveform Viewer for systemc development


thomas.haber

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SystemC, as it is right now, can create perfectly nice VCD

 files that can be manipulated easily with GTKWave. One

issue that crops up with using a number of tools is that

the learning curve to use them effectively is steep, and

often the user is distracted from the real problem to be

solved. 

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yes i agree, one of the ideas was that when i use eclipse (and just IF using eclipse),

its a nice idea to have a waveviewer inside -- so in the same style like the rest.

No change between application , similar shortcuts , and so on.

 

ähh forgotten. I added a video, so no need to install to get an impression :   http://toem.de/index.php/impulse

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  • 1 month later...

Hello Thomas,

 

Finding documentation on these tool-dependent trace file formats can be difficult.

 

There's also the WDB format used by Mentor Graphics in its digital and mixed-signal simulators and displayed by EZwave, which can trace digital and analog signals in the same database file. I'm not aware of any documentation for this file format except for an API to access the file format.

 

I'm aware of the following documented data formats, which support time series of data:

Hierarchical Data Format (HDF5): http://en.wikipedia.org/wiki/Hierarchical_Data_Format

NetCDF: http://en.wikipedia.org/wiki/NetCDF

 

Both formats are more generic. However, at the moment, they not supported by SystemC or SystemC AMS.

 

Best regards, Torsten

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  • 3 months later...

Hi Summit,

 

I put some comments into your request:

 
 
#0000023: Combining single bit signals into multi-bit signal
#Would be great if we can combine many single bit signal into multibit signal
 
Yes i'm thinking about a group feature.
But usually bit signals in vcd that belong to a group ([3]) are allready combined by default!
 
#0000022: Splitting Multibit Signals into constituent bits
#Would be great if there is any mechanism to split every N-bit signals to N individual bits
 
This is allready possible but not auomatically for a whole bus.
You can copy the config and do a selection of the bits you want to see (logic data tab).
An ungroup feature would make it automatically.
 
#0000021: Hierarchy solver for VCD
#VCD signals are shown as U_ab.U_hb.U......, can you please add a mechanism which will automaticall resolve this into hierarchy.
 
 
This i don't understand.
The VCD signal allready contains a hierarchy structure.
This is used in impulse.
 
#0000020: Conversion of any data-type to analog data-type
#Feature of conversion any signal to analog signal (interpolated or step) upon right click. Very important for signal processing systems.
 
 
This is possible (see logic data tab)
 
#0000019: Style and signedness on Right click over signal
#Would be great if data style and signedness can be available within right click over the signal. 
 
Does it mean you want an indicator which format is shown ? eg 0001H ,  0001O , 0001B (for hex,octal,binary).
Signed and unsigned should not be misleading ?!?
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Hi Thomas,

 

 

#0000023: Combining single bit signals into multi-bit signal #Would be great if we can combine many single bit signal into multibit signal Yes i'm thinking about a group feature. But usually bit signals in vcd that belong to a group ([3]) are allready combined by default!

 

Thanks for that. I know commercial tracers does this and hence there should be a way to do this. Let us think together.

 

 

#0000022: Splitting Multibit Signals into constituent bits #Would be great if there is any mechanism to split every N-bit signals to N individual bits This is allready possible but not auomatically for a whole bus. You can copy the config and do a selection of the bits you want to see (logic data tab). An ungroup feature would make it automatically.

 

Thanks for the info. Sorry I missed that.

 

 

#0000021: Hierarchy solver for VCD #VCD signals are shown as U_ab.U_hb.U......, can you please add a mechanism which will automaticall resolve this into hierarchy. This i don't understand. The VCD signal allready contains a hierarchy structure. This is used in impulse.

 

What I meant is that for any vcd file every signal is under directory SystemC (in the hierarchy pane) and if you select SystemC folder, every signals from every hierarchy is available. This makes the situation complicated. However, there are different hierarchies available. Would be great if there are justified subfolder tree under SystemC directory so that signal selection is easy during debug.

 

 

#0000020: Conversion of any data-type to analog data-type #Feature of conversion any signal to analog signal (interpolated or step) upon right click. Very important for signal processing systems. This is possible (see logic data tab)

 

Yes this is possible, but with many clicks. I would be looking for a less click and hence the options should be available within one click (in 2nd click the operation is done).

 

 

#0000019: Style and signedness on Right click over signal #Would be great if data style and signedness can be available within right click over the signal.  Does it mean you want an indicator which format is shown ? eg 0001H ,  0001O , 0001B (for hex,octal,binary). Signed and unsigned should not be misleading ?!?  

 

Same as above.

 

Regards, Sumit

 

 

 

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#0000021: 

Now i understand. But its a problem to solve. Usually simulator put the struture into the vcd and then you see a tree of elements.

But SystemC does not by default it seems.

 

$scope module SystemC $end

$var wire   32  aaa  top.irx_hsdpa_top.HSI_CLC_REG [31:0]  $end
.....
 

Don't know why. Maybe its possible. I will open a thread about it !

If there is a structure you see it. And then you can copy whole structures into the view.

 

Now i also understand your request about a new view.

Usually you have a structure and in the signal view you can collapse and open parts of it.

Additionally you can define multiple configurations and switch thwem on the same file.

 

#0000020

You know that you can slect multiple signals and press enter to open the dialog for all of them ?

That not more than 3 clicks and presses for N Signals.

 

#0000019

Ok you want to change it (see 20). I thought you want a clear indicator what is currently displayed. Would it make sense ?

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Hi Thomas,

 

Hope I am keeping you busy by flooding "New feature request". I am happy that I am able to keep you busy.

 

Can you make impulse reading a XML file OR some "Other file" which contain connection and hierarchy information about SoC fabric ? Have some more idea to employ impulse for some other job also.

 

Regards, Sumit

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#0000021: 

Now i understand. But its a problem to solve. Usually simulator put the struture into the vcd and then you see a tree of elements.

But SystemC does not by default it seems.

 

$scope module SystemC $end

$var wire   32  aaa  top.irx_hsdpa_top.HSI_CLC_REG [31:0]  $end
.....
 

Don't know why. Maybe its possible. I will open a thread about it !

If there is a structure you see it. And then you can copy whole structures into the view.

 

 

Just check out vcd2lxt of gtkwave. It resolves this hierarchy conflict of SystemC vcd files

 

Regards, Sumit

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>>Hope I am keeping you busy by flooding "New feature request". I am happy that I am able to keep you busy.

 

>>Can you make impulse reading a XML file OR some "Other file" which contain connection and hierarchy information about SoC fabric ? Have some more idea to employ impulse for some other job also.

 

 

I don't understand this. Could you please explain.

 

Best Regards,

thomas

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>>Hope I am keeping you busy by flooding "New feature request". I am happy that I am able to keep you busy.

 

Just a conversation opener.

 

>>Can you make impulse reading a XML file OR some "Other file" which contain connection and hierarchy information about SoC fabric ? Have some more idea to employ impulse for some other job also.

 

You can employ Impulse not only as a signal debugger but also as a SoC performance analyzer (at a very high abstraction level) and debugger. In order to do this impulse first should understand the design it is going to analyze and/or debug. In order to do it for an IC/SoC it needs to know IC/SoC module hierarchy and connection diagram and build an internal data structure which makes it ready for that which on query should return the answer to the debugger. XML files can be written which can contain module, sub-module and connection (signal and transactor) information. I have a wish impulse understanding this structure in order to plan SoC/IC analysis and debug capabilities.

 

Regards, Sumit

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I read the full text in the isue and i think i understand it better now.

 

The problem is that anybody want it in his special mode :-) . 
My personal view and my approach is that i want you and anybody to enable as much as possible,
but i can not implement everthing.
Solution is to enable different forms of extensions.
This is what i started some time ago.
 
This has also to do with another isses about statistical informations.
There will be an extention to calc you own statistics.
I was also thinking to combine with eclipse report engine and its charts !
 
thanks,
thomas
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I probably will not implement, but but your wishes help me to understand the needs !!

So they will get into the extension interfaces.

Please go on !

 

Java and eclipse makes it possible that you can add a lot with real low effort.

I started a series about extension intercaces last week.

 

http://toem.de/index.php/projects/impulse/articles

 

regards,

thomas

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  • 2 weeks later...

Dear Thomas,

 

Thanks for the update. I have downloaded Impulse 0.5.15 and found that hierarchy solver for vcd is working :). However I have found following issues with the completed requests which I raised earlier:

 

1. Select-All feature : Select all works everywhere apart from where it is mostly needed, the signal selection pane (left bottom pane which shows signals in a particular hierarchy).

 

2.  Impulse first drawing : The feature works, thanks for that. But now it includes some values which are not visible. I would be happy if every smallest possible changes are visible.

 

This is a great work. I do not see any commercial viewer (and my experience is with only one EDA company) solves VCD hierarchy which impulse does.

 

With the statistics work started, you have taken a big load on yourself. Good luck with it and please let me know if you need help on the way.

 

Please keep up the good work.

Regards, Sumit

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>>1. Select-All feature : Select all works everywhere apart from where it is mostly needed, the signal selection pane (left bottom pane which shows signals in a particular hierarchy).

Yes you are right.

 

>> 2.  Impulse first drawing : The feature works, thanks for that. But now it includes some values which are not visible. I would be happy if every smallest possible changes are visible.

Do you have an example - example file.

 

>> With the statistics work started, you have taken a big load on yourself. Good luck with it and please let me know if you need help on the way.

I focus on means. Not on implementing all possible statistical operations. So ther will be an outcome quite soon.

It shall be possible that user can implement their own functions.

But i need to know what can be possible requirements.

And i will implement  a couple of maybe 10 general purpose function (your input is welcome).

 

 

regards,

thomas

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  • 2 weeks later...

Hi Sumit and Torsten,

 

0.5.16 is out. It has a new View "Signal Table" that allows to 

* sort 

* filter

* view data (columns)

 

The input of the table can be bound to

* the current editor

* selection of a view (explorer)

* fixed

 

The displayed contents can be 

* the slected element

* its children

* all children below (tribe)

 

Also new are first means to modify (edit) signal files by modifying its hierarchy (copy/paste).

 

regards,

thomas

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